Re: [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes

2019-02-26 Thread Amed Magdy
> > >> > It seems to me that the C extension can be enabled at any point, since >> if C is >> > off, you know that the next insn is aligned modulo 4. >> > >> > > > Ok, This is mostly right. When C extension is enabled 32-bit base > instructions can be aligned on 2 bytes boundaries instead of 4 byt

Re: [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes

2019-02-25 Thread Amed Magdy
> > It seems to me that the C extension can be enabled at any point, since > if C is > > off, you know that the next insn is aligned modulo 4. > > > Ok, This is mostly right. When C extension is enabled 32-bit base instructions can be aligned on 2 bytes boundaries instead of 4 bytes only. So mult

Re: [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes

2019-02-25 Thread Eric Blake
On 2/24/19 2:07 AM, Amed Magdy wrote: > Thank you so much, Eric. > > Sorry about this unclear description. > I forgot to fix user name in git configuration before submitting the patch. > > Sorry about any inconvenience. Don't worry about it. We were all once first-time contributors, and it can b

Re: [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes

2019-02-24 Thread Richard Henderson
On 2/23/19 11:57 PM, Amed Magdy wrote: > Thank you for your review and feedback, Richard. > As Eric mentioned, this is the first time contribution. I have been exploring > Qemu for some time and try to understand main flow, internals, ..etc. > >>  You cannot manipulate env like this during transla

Re: [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes

2019-02-24 Thread Amed Magdy
Thank you so much, Eric. Sorry about this unclear description. I forgot to fix user name in git configuration before submitting the patch. Sorry about any inconvenience. Thanks, Ahmed On Sat, 23 Feb 2019 at 23:46, Eric Blake wrote: > On 2/22/19 10:25 AM, amagdy.af...@gmail.com wrote: > > From:

Re: [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes

2019-02-23 Thread Amed Magdy
Thank you for your review and feedback, Richard. As Eric mentioned, this is the first time contribution. I have been exploring Qemu for some time and try to understand main flow, internals, ..etc. > You cannot manipulate env like this during translation. > Neither the write to env->pc_next nor

Re: [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes

2019-02-23 Thread Eric Blake
On 2/22/19 10:25 AM, amagdy.af...@gmail.com wrote: > From: ahmed_magdy > > Signed-off-by: ahmed_magdy This appears to be your first contribution to qemu. Welcome to the community! Typically, a Signed-off-by designation should be a proper name (what you would sign a legal document with, as it h

Re: [Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes

2019-02-22 Thread Richard Henderson
On 2/22/19 8:25 AM, amagdy.af...@gmail.com wrote: > @@ -373,9 +373,10 @@ static int write_misa(CPURISCVState *env, int csrno, > target_ulong val) > } > > /* Suppress 'C' if next instruction is not aligned > - TODO: this should check next_pc */ > -if ((val & RVC) && (GETPC() &

[Qemu-devel] [PATCH] riscv: Add proper alignment check and pending 'C' extension upon misa writes

2019-02-22 Thread amagdy . afifi
From: ahmed_magdy Signed-off-by: ahmed_magdy --- target/riscv/cpu.h | 2 ++ target/riscv/csr.c | 5 +++-- target/riscv/translate.c | 14 ++ 3 files changed, 15 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a269c07..b49bdb3 10