On 14 December 2013 10:58, Paolo Bonzini wrote:
> Il 13/12/2013 20:18, Scott Wood ha scritto:
>>> Also are you sure flush_icache_range()
>>> works correctly when multiple threads (multiple vCPUs,
>>> potentially executing on different host CPUs) are involved?
>>
>> On PPC these cache operations br
Il 13/12/2013 20:18, Scott Wood ha scritto:
>> Also are you sure flush_icache_range()
>> works correctly when multiple threads (multiple vCPUs,
>> potentially executing on different host CPUs) are involved?
>
> On PPC these cache operations broadcast, and are the architecturally
> defined way of d
On Wed, 2013-12-11 at 13:56 +, Peter Maydell wrote:
> On 11 December 2013 13:23, Alexander Graf wrote:
> > The guest expects that its data and instruction cache view of the world
> > is 100% consistent when it initially boots. This works just fine on
> > initial rom population for the first bo
On 11.12.2013, at 15:07, Peter Maydell wrote:
> But these are (emulated) ROMs, not an emulated bootloader.
> They ought to work like actual ROMs: QEMU as the emulator
> of the system/devices provides the contents of physical address
> space; KVM as the emulator of the CPU provides a CPU which
> do
> On 11.12.2013, at 16:15, Alexander Graf < ag...@suse.de > wrote:
>
> Well, this really is a simplified view of the world.
>
> On real hardware the system boots up with caches disabled. Firmware is
> then responsible for enabling caches and flushing things as it goes.
> Firmware loads the kernel
an Mihai
> Claudiu-B02008
> Subject: Re: [Qemu-devel] [PATCH] roms: Flush icache when writing roms to
> guest memory
>
> On 11 December 2013 13:35, Alexander Graf wrote:
> > How would KVM know when things changed inside of a memory region?
> > It's up to user s
On 11.12.2013, at 15:25, Peter Maydell wrote:
> On 11 December 2013 14:18, mihai.cara...@freescale.com
> wrote:
>>> From: Peter Maydell [mailto:peter.mayd...@linaro.org]
>>> If the architecture spec says that a freshly reset physical CPU has
>>> coherent icache and dcache, then resetting the vC
On 11 December 2013 14:18, mihai.cara...@freescale.com
wrote:
>> From: Peter Maydell [mailto:peter.mayd...@linaro.org]
>> If the architecture spec says that a freshly reset physical CPU has
>> coherent icache and dcache, then resetting the vCPU should also
>> ensure the icache and dcache are coher
On 11.12.2013, at 15:03, Paolo Bonzini wrote:
> Il 11/12/2013 14:35, Alexander Graf ha scritto:
>> +if (kvm_enabled()) {
>> +/*
>> + * The guest may want to directly execute from the rom
>> region,
>> + * so we bett
On 11.12.2013, at 15:07, Peter Maydell wrote:
> On 11 December 2013 13:35, Alexander Graf wrote:
>> How would KVM know when things changed inside of a memory region?
>> It's up to user space to manage the contents of a memory region, no?
>
> If the architecture spec says that a freshly reset p
On 11 December 2013 13:35, Alexander Graf wrote:
> How would KVM know when things changed inside of a memory region?
> It's up to user space to manage the contents of a memory region, no?
If the architecture spec says that a freshly reset physical CPU has
coherent icache and dcache, then resettin
Il 11/12/2013 14:35, Alexander Graf ha scritto:
>>> >> +if (kvm_enabled()) {
>>> >> +/*
>>> >> + * The guest may want to directly execute from the rom
>>> >> region,
>>> >> + * so we better invalidate its icache
>>> >> + *
On 11 December 2013 13:23, Alexander Graf wrote:
> The guest expects that its data and instruction cache view of the world
> is 100% consistent when it initially boots. This works just fine on
> initial rom population for the first boot.
>
> However, when we reboot and then repopulate the rom regi
On 11.12.2013, at 14:27, Paolo Bonzini wrote:
> Il 11/12/2013 14:23, Alexander Graf ha scritto:
>> +if (kvm_enabled()) {
>> +/*
>> + * The guest may want to directly execute from the rom
>> region,
>> + * so we better invalidate its ic
Il 11/12/2013 14:23, Alexander Graf ha scritto:
> +if (kvm_enabled()) {
> +/*
> + * The guest may want to directly execute from the rom
> region,
> + * so we better invalidate its icache
> + */
> +flush_ica
We use the rom infrastructure to write firmware and/or initial kernel
blobs into guest address space. So we're essentially the layer before
the first code that gets executed inside the guest.
The guest expects that its data and instruction cache view of the world
is 100% consistent when it initial
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