Re: [Qemu-devel] [PATCH] target/riscv: Zero extend the inputs of divuw and remuw

On 3/21/19 7:59 AM, Palmer Dabbelt wrote: > While running the GCC test suite against 4.0.0-rc0, Kito found a > regression introduced by the decodetree conversion that caused divuw and > remuw to sign-extend their inputs. The ISA manual says they are > supposed to be zero extended: > > DIVW an

Re: [Qemu-devel] [PATCH] target/riscv: Zero extend the inputs of divuw and remuw

Verified with gcc testsuite on rv64gc, no new regression introduced, and get less fails. Palmer Dabbelt 於 2019年3月21日 週四，22:59寫道： > While running the GCC test suite against 4.0.0-rc0, Kito found a > regression introduced by the decodetree conversion that caused divuw and > remuw to sign-extend the

[Qemu-devel] [PATCH] target/riscv: Zero extend the inputs of divuw and remuw

While running the GCC test suite against 4.0.0-rc0, Kito found a regression introduced by the decodetree conversion that caused divuw and remuw to sign-extend their inputs. The ISA manual says they are supposed to be zero extended: DIVW and DIVUW instructions are only valid for RV64, and divi