Re: [Qemu-devel] [PATCH] target-arm: A64: Correct handling of UXN bit.

2014-06-10 Thread Claudio Fontana
This patch fixes my issue with page tables switching on OSv guest. Thank you all! Tested-by: Claudio Fontana claudio.font...@huawei.com On 08.06.2014 15:53, Ian Campbell wrote: In v8 page tables bit 54 in the PTE is UXN in the EL0/EL1 translation regimes and XN elsewhere. In v7 the bit is

Re: [Qemu-devel] [PATCH] target-arm: A64: Correct handling of UXN bit.

2014-06-09 Thread Peter Maydell
On 8 June 2014 14:53, Ian Campbell i...@hellion.org.uk wrote: In v8 page tables bit 54 in the PTE is UXN in the EL0/EL1 translation regimes and XN elsewhere. In v7 the bit is always XN. Since we only emulate EL0/EL1 we can just treat this bit as UXN whenever we are in v8 mode. Also correctly

Re: [Qemu-devel] [PATCH] target-arm: A64: Correct handling of UXN bit.

2014-06-09 Thread Edgar E. Iglesias
On Mon, Jun 09, 2014 at 02:40:59PM +0100, Peter Maydell wrote: On 8 June 2014 14:53, Ian Campbell i...@hellion.org.uk wrote: In v8 page tables bit 54 in the PTE is UXN in the EL0/EL1 translation regimes and XN elsewhere. In v7 the bit is always XN. Since we only emulate EL0/EL1 we can

[Qemu-devel] [PATCH] target-arm: A64: Correct handling of UXN bit.

2014-06-08 Thread Ian Campbell
In v8 page tables bit 54 in the PTE is UXN in the EL0/EL1 translation regimes and XN elsewhere. In v7 the bit is always XN. Since we only emulate EL0/EL1 we can just treat this bit as UXN whenever we are in v8 mode. Also correctly extract the upper attributes from the PTE entry, the v8 version