On Tue, Feb 22, 2011 at 06:19:43PM +, Peter Maydell wrote:
Newer ARM kernels try to probe for whether the CPU has hardware breakpoint
support. For this to work QEMU has to implement a minimal set of the cp14
debug registers. The architecture requires v7 cores to implement debug
and so
On 22 February 2011 18:19, Peter Maydell peter.mayd...@linaro.org wrote:
+ tmp = tcg_const_i32(0);
+ store_reg(s, rt, tmp);
This generates spurious resource leak warnings, because
store_reg() calls dead_tmp() so you can't store anything
you didn't get from new_tmp().
I
Newer ARM kernels try to probe for whether the CPU has hardware breakpoint
support. For this to work QEMU has to implement a minimal set of the cp14
debug registers. The architecture requires v7 cores to implement debug
and so there is no defined way to report its absence; however in practice
