Re: [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers

2017-02-08 Thread Richard Henderson
On 02/08/2017 06:01 AM, Stafford Horne wrote: On Mon, Feb 06, 2017 at 09:53:26PM -0800, Richard Henderson wrote: On 02/01/2017 02:04 AM, Stafford Horne wrote: For kernel builds I have created toolchain binaries here: http://shorne.noip.me/crosstool/files/bin/x86_64/5.4.0/ These should

Re: [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers

2017-02-08 Thread Stafford Horne
Hello, On Wed, Feb 08, 2017 at 11:01:20PM +0900, Stafford Horne wrote: > On Mon, Feb 06, 2017 at 09:53:26PM -0800, Richard Henderson wrote: > > On 02/01/2017 02:04 AM, Stafford Horne wrote: > > > For kernel builds I have created toolchain binaries here: > > > > > >

Re: [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers

2017-02-08 Thread Stafford Horne
On Mon, Feb 06, 2017 at 09:53:26PM -0800, Richard Henderson wrote: > On 02/01/2017 02:04 AM, Stafford Horne wrote: > > For kernel builds I have created toolchain binaries here: > > > > http://shorne.noip.me/crosstool/files/bin/x86_64/5.4.0/ > > > > These should work. > > This gdb crashes on

Re: [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers

2017-02-06 Thread Richard Henderson
On 02/01/2017 02:04 AM, Stafford Horne wrote: For kernel builds I have created toolchain binaries here: http://shorne.noip.me/crosstool/files/bin/x86_64/5.4.0/ These should work. This gdb crashes on the first "stepi" that I issue. To reproduce, $ cat z.c int main() { return 0; } $

Re: [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers

2017-02-06 Thread Richard Henderson
On 02/03/2017 07:14 AM, Stafford Horne wrote: I tried your tgt-or1k-2 branch with my latest kernel and have no issues. Ok, excellent, thanks. I'll send a pull for that branch then. r~

Re: [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers

2017-02-03 Thread Stafford Horne
On Thu, Feb 02, 2017 at 11:34:55PM +0900, Stafford Horne wrote: > On Wed, Feb 01, 2017 at 10:15:54AM -0800, Richard Henderson wrote: > > On 02/01/2017 02:04 AM, Stafford Horne wrote: > > > On Thu, Jan 26, 2017 at 09:26:55AM -0800, Richard Henderson wrote: > > >> On 01/26/2017 05:12 AM, Stafford

Re: [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers

2017-02-02 Thread Stafford Horne
On Wed, Feb 01, 2017 at 10:15:54AM -0800, Richard Henderson wrote: > On 02/01/2017 02:04 AM, Stafford Horne wrote: > > On Thu, Jan 26, 2017 at 09:26:55AM -0800, Richard Henderson wrote: > >> On 01/26/2017 05:12 AM, Stafford Horne wrote: > >>> I just sent you a mail with a link to my kernel for

Re: [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers

2017-02-01 Thread Richard Henderson
On 02/01/2017 02:04 AM, Stafford Horne wrote: > On Thu, Jan 26, 2017 at 09:26:55AM -0800, Richard Henderson wrote: >> On 01/26/2017 05:12 AM, Stafford Horne wrote: >>> I just sent you a mail with a link to my kernel for download. >>> >>> One thing I noticed is you passed '-append console=ttyS0' I

Re: [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers

2017-02-01 Thread Stafford Horne
On Thu, Jan 26, 2017 at 09:26:55AM -0800, Richard Henderson wrote: > On 01/26/2017 05:12 AM, Stafford Horne wrote: > > I just sent you a mail with a link to my kernel for download. > > > > One thing I noticed is you passed '-append console=ttyS0' I think that > > does nothing on openrisc since as

Re: [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers

2017-01-26 Thread Stafford Horne
On Thu, Jan 26, 2017 at 09:26:55AM -0800, Richard Henderson wrote: > On 01/26/2017 05:12 AM, Stafford Horne wrote: > > I just sent you a mail with a link to my kernel for download. > > > > One thing I noticed is you passed '-append console=ttyS0' I think that > > does nothing on openrisc since as

Re: [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers

2017-01-26 Thread Richard Henderson
On 01/26/2017 05:12 AM, Stafford Horne wrote: I just sent you a mail with a link to my kernel for download. One thing I noticed is you passed '-append console=ttyS0' I think that does nothing on openrisc since as far as I know openrisc only gets boot params from the device tree file. I tried

Re: [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers

2017-01-26 Thread Stafford Horne
On Wed, Jan 25, 2017 at 09:27:29AM -0800, Richard Henderson wrote: > On 01/25/2017 04:34 AM, Stafford Horne wrote: > > Hmm, I just tried your qemu branch and mine: > > > > g...@github.com:stffrdhrn/qemu.git or1k-fix-sigill > > > > Both of them were able to boot fine. > > > > The

Re: [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers

2017-01-25 Thread Richard Henderson
On 01/25/2017 04:34 AM, Stafford Horne wrote: > Hmm, I just tried your qemu branch and mine: > > g...@github.com:stffrdhrn/qemu.git or1k-fix-sigill > > Both of them were able to boot fine. > > The opencores,or1200-rtlsvn481 cpu node is in the or1ksim device tree > definition. Are you sure

Re: [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers

2017-01-25 Thread Stafford Horne
On Tue, Jan 24, 2017 at 10:32:03AM -0800, Richard Henderson wrote: > On 01/24/2017 02:26 AM, Stafford Horne wrote: > > If you are having problems booting, both mainline (4.10-rc5) and > > linux-next (i.e. next-201701124) should be able to boot. i.e. > > > > export ARCH=openrisc > > make

Re: [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers

2017-01-24 Thread Richard Henderson
On 01/24/2017 02:26 AM, Stafford Horne wrote: > If you are having problems booting, both mainline (4.10-rc5) and > linux-next (i.e. next-201701124) should be able to boot. i.e. > > export ARCH=openrisc > make defconfig # defconfig works fine on qemu > > # make any updates to

Re: [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers

2017-01-24 Thread Stafford Horne
On Mon, Jan 23, 2017 at 10:08:47AM -0800, Richard Henderson wrote: > On 01/20/2017 08:39 AM, Stafford Horne wrote: > > (+CC Rth) > > > > I believe you also have some experience with openrisc. Any thought on > > the below? > > > > On Sat, Jan 14, 2017 at 05:04:35PM +0900, Stafford Horne wrote: >

Re: [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers

2017-01-23 Thread Richard Henderson
On 01/20/2017 08:39 AM, Stafford Horne wrote: > (+CC Rth) > > I believe you also have some experience with openrisc. Any thought on > the below? > > On Sat, Jan 14, 2017 at 05:04:35PM +0900, Stafford Horne wrote: >> Hello, >> >> On Sat, Jan 14, 2017 at 12:29:32PM +0800, Jia Liu wrote: >>> Hi

Re: [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers

2017-01-20 Thread Stafford Horne
(+CC Rth) I believe you also have some experience with openrisc. Any thought on the below? On Sat, Jan 14, 2017 at 05:04:35PM +0900, Stafford Horne wrote: > Hello, > > On Sat, Jan 14, 2017 at 12:29:32PM +0800, Jia Liu wrote: > > Hi all, > > > > On Sat, Jan 14, 2017 at 6:02 AM, Stafford Horne

Re: [Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers

2017-01-14 Thread Stafford Horne
Hello, On Sat, Jan 14, 2017 at 12:29:32PM +0800, Jia Liu wrote: > Hi all, > > On Sat, Jan 14, 2017 at 6:02 AM, Stafford Horne wrote: > > Hello, > > > > Sorry for the duplicate. There was an issue with my copy to qemu-devel > > group. Resent to everyone with proper cc to

[Qemu-devel] [PATCH] target-openrisc: Fix exception handling status registers

2017-01-13 Thread Stafford Horne
I am working on testing instruction emulation patches for the linux kernel. During testing I found these 2 issues: - sets DSX (delay slot exception) but never clears it - EEAR for illegal insns should point to the bad exception (as per openrisc spec) but its not This patch fixes these two