On ARM, the FPSCR FZ bit (which controls whether denormals should be flushed to zero) is supposed to cause this flushing to occur both when the output of a calculation is a denormal (already implemented in softfloat) and also when the input to a calculation is a denormal (not implemented, as noted by a FIXME comment).
This patchset adds the support to softfloat for flushing denormals on input. This is controlled using a new status flag to enable it (so that CPUs which only flush on output continue to work). There is a new exception status bit to indicate when input flushing has happened (because on ARM it is reported via a different FPSCR bit to that used when an output denormal is flushed to zero). I have deliberately only implemented this for input float32 and float64 values because that is what ARM requires (on ARM float16 inputs must not be flushed to zero and floatx80 and float128 are not used) so other changes would be totally untested code. Existing CPUs should be unaffected as there is no behaviour change unless the mode is enabled. (I suspect that MIPS should be able to use this to implement the FCSR FO bit if desired.) Tested using random instruction generation for vadd/vsub/vmul/vdiv with the FPSCR FZ bit set. Peter Maydell (2): softfloat: Implement flushing input denormals to zero ARM: wire up the softfloat flush_input_to_zero flag fpu/softfloat.c | 104 ++++++++++++++++++++++++++++++++++++++++++++++++++- fpu/softfloat.h | 22 ++++++++++- target-arm/helper.c | 10 ++++- 3 files changed, 131 insertions(+), 5 deletions(-)
