On 21.05.2011 14:46, Aurelien Jarno wrote:
We definitely need to rewrite/improve the register allocator to save a
global back to memory when it is not used later in the TB. I am
currently working on that, I hope to have something ready soon.
I think I have this done already. The patches need cl
On Fri, May 20, 2011 at 09:35:08PM +0200, Aurelien Jarno wrote:
> On Fri, May 20, 2011 at 04:39:27PM +0400, Kirill Batuzov wrote:
> > This series implements some basic machine-independent optimizations. They
> > simplify code and allow liveness analysis do it's work better.
> >
> > Suppose we hav
On 05/20/2011 11:35 PM, Aurelien Jarno wrote:
>
> On Fri, May 20, 2011 at 04:39:27PM +0400, Kirill Batuzov wrote:
>> This series implements some basic machine-independent optimizations. They
>> simplify code and allow liveness analysis do it's work better.
>>
>> Suppose we have following ARM code
On Sat, May 21, 2011 at 11:37:49AM +0200, Laurent Desnogues wrote:
> On Sat, May 21, 2011 at 1:31 AM, Andreas Färber
> wrote:
> [...]
> > Has anyone evaluated reusing LLVM optimization passes for TCG? Or maybe
> > GIMPL if there's an equivalent?
>
> IMHO the qemu_ld/st semantics and the size of
On Sat, May 21, 2011 at 1:31 AM, Andreas Färber wrote:
[...]
> Has anyone evaluated reusing LLVM optimization passes for TCG? Or maybe
> GIMPL if there's an equivalent?
IMHO the qemu_ld/st semantics and the size of TB blocks
will always limit the usefulness of more involved
optimizations than wha
Am 20.05.2011 um 21:37 schrieb Aurelien Jarno:
On Fri, May 20, 2011 at 10:50:49AM -0700, Richard Henderson wrote:
On 05/20/2011 05:39 AM, Kirill Batuzov wrote:
This series implements some basic machine-independent
optimizations. They
simplify code and allow liveness analysis do it's work be
On Fri, May 20, 2011 at 10:50:49AM -0700, Richard Henderson wrote:
> On 05/20/2011 05:39 AM, Kirill Batuzov wrote:
> > This series implements some basic machine-independent optimizations. They
> > simplify code and allow liveness analysis do it's work better.
> >
> > Suppose we have following ARM
On Fri, May 20, 2011 at 04:39:27PM +0400, Kirill Batuzov wrote:
> This series implements some basic machine-independent optimizations. They
> simplify code and allow liveness analysis do it's work better.
>
> Suppose we have following ARM code:
>
> movwr12, #0xb6db
> movtr12, #0xdb6d
>
On 05/20/2011 05:39 AM, Kirill Batuzov wrote:
> This series implements some basic machine-independent optimizations. They
> simplify code and allow liveness analysis do it's work better.
>
> Suppose we have following ARM code:
>
> movwr12, #0xb6db
> movtr12, #0xdb6d
>
> In TCG before
This series implements some basic machine-independent optimizations. They
simplify code and allow liveness analysis do it's work better.
Suppose we have following ARM code:
movwr12, #0xb6db
movtr12, #0xdb6d
In TCG before optimizations we'll have:
movi_i32 tmp8,$0xb6db
mov_i32 r12,t
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