The way we're currently modeling mmio is too simplified. We assume that
every device has the same endianness as the target CPU. In reality,
most devices are little endian (all PCI and ISA ones I'm aware of). Some
are big endian (special system devices) and a very little fraction is
target native en
The way we're currently modeling mmio is too simplified. We assume that
every device has the same endianness as the target CPU. In reality,
most devices are little endian (all PCI and ISA ones I'm aware of). Some
are big endian (special system devices) and a very little fraction is
target native en
On 28.11.2010, at 09:12, Gleb Natapov wrote:
> On Thu, Nov 25, 2010 at 08:35:41AM +0100, Alexander Graf wrote:
>> The way we're currently modeling mmio is too simplified. We assume that
>> every device has the same endianness as the target CPU. In reality,
>> most devices are little endian (all P
On Thu, Nov 25, 2010 at 08:35:41AM +0100, Alexander Graf wrote:
> The way we're currently modeling mmio is too simplified. We assume that
> every device has the same endianness as the target CPU. In reality,
> most devices are little endian (all PCI and ISA ones I'm aware of). Some
> are big endian
> > Switching endianness of a CPU generally does not effect the endianness of
> > the CPU/peripheral busses. It makes the CPU byteswap accesses before
> > they are seen by either memory or devices.
> >
> > In theory it might be possible to avoid redundant byteswaps if you're
> > really clever. I
On Fri, Nov 26, 2010 at 11:47 PM, Paul Brook wrote:
>> > diff --git a/exec.c b/exec.c
>> > index db9ff55..f54a360 100644
>> > --- a/exec.c
>> > +++ b/exec.c
>> >
>> > @@ -3370,6 +3474,22 @@ static int cpu_register_io_memory_fixed(int
>> > io_index,
>> >
>> > }
>> > io_mem_opaque[io_index]
> > diff --git a/exec.c b/exec.c
> > index db9ff55..f54a360 100644
> > --- a/exec.c
> > +++ b/exec.c
> >
> > @@ -3370,6 +3474,22 @@ static int cpu_register_io_memory_fixed(int
> > io_index,
> >
> > }
> > io_mem_opaque[io_index] = opaque;
> >
> > +switch (endian) {
> > +case DEVIC
On 26 November 2010 23:00, Andreas Färber wrote:
> Am 25.11.2010 um 08:35 schrieb Alexander Graf:
>> + switch (endian) {
>> + case DEVICE_BIG_ENDIAN:
>> +#ifndef TARGET_WORDS_BIGENDIAN
>> + swapendian_init(io_index);
>> +#endif
>> + break;
>
> So basically, you just moved the #
On 27.11.2010, at 00:00, Andreas Färber wrote:
> Am 25.11.2010 um 08:35 schrieb Alexander Graf:
>
>> The way we're currently modeling mmio is too simplified. We assume that
>> every device has the same endianness as the target CPU. In reality,
>> most devices are little endian (all PCI and ISA o
Am 25.11.2010 um 08:35 schrieb Alexander Graf:
The way we're currently modeling mmio is too simplified. We assume
that
every device has the same endianness as the target CPU. In reality,
most devices are little endian (all PCI and ISA ones I'm aware of).
Some
are big endian (special system
The way we're currently modeling mmio is too simplified. We assume that
every device has the same endianness as the target CPU. In reality,
most devices are little endian (all PCI and ISA ones I'm aware of). Some
are big endian (special system devices) and a very little fraction is
target native en
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