On 04/06/2017 11:54 PM, Benjamin Herrenschmidt wrote:
> On Thu, 2017-04-06 at 14:44 +0200, Cédric Le Goater wrote:
>> May be we could move that under the LPC object even if it is not
>> strictly
>> correct from a HW pov ?
>
> I'm not fan of this. It's really not part of the LPC controller and
> i
On Thu, 2017-04-06 at 14:44 +0200, Cédric Le Goater wrote:
> May be we could move that under the LPC object even if it is not
> strictly
> correct from a HW pov ?
I'm not fan of this. It's really not part of the LPC controller and
it's specific to a certain crop of P8 machines.
Cheers,
Ben.
On 04/06/2017 04:02 AM, David Gibson wrote:
> On Wed, Apr 05, 2017 at 02:41:28PM +0200, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt
>>
>> It adds the Naples chip which supports proper LPC interrupts via the
>> LPC controller rather than via an external CPLD.
>>
>> Signed-off-by: Benjam
On 04/06/2017 04:02 AM, David Gibson wrote:
> On Wed, Apr 05, 2017 at 02:41:28PM +0200, Cédric Le Goater wrote:
>> From: Benjamin Herrenschmidt
>>
>> It adds the Naples chip which supports proper LPC interrupts via the
>> LPC controller rather than via an external CPLD.
>>
>> Signed-off-by: Benjam
On Wed, Apr 05, 2017 at 02:41:28PM +0200, Cédric Le Goater wrote:
> From: Benjamin Herrenschmidt
>
> It adds the Naples chip which supports proper LPC interrupts via the
> LPC controller rather than via an external CPLD.
>
> Signed-off-by: Benjamin Herrenschmidt
> [clg: - updated for qemu-2.9
>
From: Benjamin Herrenschmidt
It adds the Naples chip which supports proper LPC interrupts via the
LPC controller rather than via an external CPLD.
Signed-off-by: Benjamin Herrenschmidt
[clg: - updated for qemu-2.9
- ported on latest PowerNV patchset ]
Signed-off-by: Cédric Le Goater
Revi
