Re: [Qemu-devel] [PATCH 04/18] target-riscv: Add framework for instruction decode

2016-09-26 Thread Richard Henderson
On 09/26/2016 03:56 AM, Sagar Karandikar wrote: +/* THIS BUILDS 13 bit imm (implicit zero is tacked on here), also note that bit + #12 is obtained in a special way to get sign extension */ +#define GET_B_IMM(inst) ((int16_t)inst >> 25) & 0x3F) << 5)\ +

[Qemu-devel] [PATCH 04/18] target-riscv: Add framework for instruction decode

2016-09-26 Thread Sagar Karandikar
Body of decode_opc with LUI, AUIPC, JAL instructions Decode table in instmap.h Signed-off-by: Sagar Karandikar --- target-riscv/instmap.h | 328 +++ target-riscv/translate.c | 64 + 2 files changed, 392 insertions(+) create mode 100644 targ