On 10/29/2013 03:41 PM, Sebastian Macke wrote:
>
> What is included in the tb hash? The virtual pc + physical page + the
> tb_flags?
> Not the mmu_index?
What's included is everything you return from cpu_get_tb_cpu_state.
Note that cs_base is an interesting case. On i386 real mode, it's
what t
On 11/01/2013 11:58 AM, Peter Maydell wrote:
>> > What is included in the tb hash? The virtual pc + physical page + the
>> > tb_flags? Not the mmu_index?
> You're right that the mmu_index is not included in the tb hash.
> Does that mean that the CPU state which determines the
> mmu_index needs to b
On 29 October 2013 22:41, Sebastian Macke wrote:
> On 29/10/2013 12:47 PM, Peter Maydell wrote:
>>
>> On 29 October 2013 19:04, Sebastian Macke wrote:
>>> /* Internal flags, delay slot flag */
>>> -#define D_FLAG1
>>> +#define D_FLAG2
>>
>> Since this set of #defines effectively is the
On 29/10/2013 12:47 PM, Peter Maydell wrote:
On 29 October 2013 19:04, Sebastian Macke wrote:
The TLB flush is not necessary as the mmu_index field
already takes care of correct memory locations.
Instead the tb flag field must be expanded that
the exception takes the correct translation block.
On 29 October 2013 19:04, Sebastian Macke wrote:
> The TLB flush is not necessary as the mmu_index field
> already takes care of correct memory locations.
> Instead the tb flag field must be expanded that
> the exception takes the correct translation block.
>
> Signed-off-by: Sebastian Macke
> --
The TLB flush is not necessary as the mmu_index field
already takes care of correct memory locations.
Instead the tb flag field must be expanded that
the exception takes the correct translation block.
Signed-off-by: Sebastian Macke
---
target-openrisc/cpu.h | 4 ++--
target-openrisc/interr
