On 10/01/2016 05:05 AM, Artyom Tarasenko wrote:
As described in Chapter 5.7.6 of the UltraSPARC Architecture 2005,
outstanding disrupting exceptions that are destined for privileged mode can only
cause a trap when the virtual processor is in nonprivileged or privileged mode
and
PSTATE.ie = 1. At
As described in Chapter 5.7.6 of the UltraSPARC Architecture 2005,
outstanding disrupting exceptions that are destined for privileged mode can only
cause a trap when the virtual processor is in nonprivileged or privileged mode
and
PSTATE.ie = 1. At all other times, they are held pending.
Signed-o
