Re: [Qemu-devel] [PATCH 08/12] target-mips: add BadInstr and BadInstrP support

2014-07-08 Thread Leon Alrae
On 19/06/2014 23:13, Aurelien Jarno wrote: I don't think this should implemented that way, as it would have a significant impact on the performances. Given we have the fault address (we fill EPC), we can fetch the corresponding opcode. There might be some code change to do for the branches, so

[Qemu-devel] [PATCH 08/12] target-mips: add BadInstr and BadInstrP support

2014-06-19 Thread Leon Alrae
BadInstr Register (CP0 Register 8, Select 1) The BadInstr register is a read-only register that capture the most recent instruction which caused an exception. BadInstrP Register (CP0 Register 8, Select 2) The BadInstrP register contains the prior branch instruction, when the faulting instruction

Re: [Qemu-devel] [PATCH 08/12] target-mips: add BadInstr and BadInstrP support

2014-06-19 Thread Aurelien Jarno
On Thu, Jun 19, 2014 at 03:45:39PM +0100, Leon Alrae wrote: BadInstr Register (CP0 Register 8, Select 1) The BadInstr register is a read-only register that capture the most recent instruction which caused an exception. BadInstrP Register (CP0 Register 8, Select 2) The BadInstrP register