On 09/26/2016 03:56 AM, Sagar Karandikar wrote:
> +static inline void gen_atomic(DisasContext *ctx, uint32_t opc,
> + int rd, int rs1, int rs2)
> +{
> +/* TODO: handle aq, rl bits? - for now just get rid of them: */
> +opc = MASK_OP_ATOMIC_NO_AQ_RL(opc);
We have alread
Signed-off-by: Sagar Karandikar
---
target-riscv/translate.c | 154 +++
1 file changed, 154 insertions(+)
diff --git a/target-riscv/translate.c b/target-riscv/translate.c
index 767cdbe..af82eab 100644
--- a/target-riscv/translate.c
+++ b/target-riscv/t
