Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit

2018-06-13 Thread Eduardo Habkost
On Wed, Jun 13, 2018 at 05:39:50PM +0100, Daniel P. Berrangé wrote: [...] > > The code that finds the AMD_SSBD and sets the 'ssbd' is: > > > > + if (cpu_has(c, X86_FEATURE_AMD_SSBD)) { > > + set_cpu_cap(c, X86_FEATURE_SSBD); > > + set_cpu_cap(c, X86_FEATURE_MSR_SP

Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit

2018-06-13 Thread Daniel P . Berrangé
On Wed, Jun 13, 2018 at 12:34:21PM -0400, Konrad Rzeszutek Wilk wrote: > On Wed, Jun 13, 2018 at 05:21:29PM +0100, Daniel P. Berrangé wrote: > > On Wed, Jun 13, 2018 at 12:09:59PM -0400, Konrad Rzeszutek Wilk wrote: > > > On Wed, Jun 13, 2018 at 11:19:49AM +0100, Daniel P. Berrangé wrote: > > > > O

Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit

2018-06-13 Thread Konrad Rzeszutek Wilk
On Wed, Jun 13, 2018 at 05:21:29PM +0100, Daniel P. Berrangé wrote: > On Wed, Jun 13, 2018 at 12:09:59PM -0400, Konrad Rzeszutek Wilk wrote: > > On Wed, Jun 13, 2018 at 11:19:49AM +0100, Daniel P. Berrangé wrote: > > > On Mon, Jun 04, 2018 at 04:22:05PM -0400, Konrad Rzeszutek Wilk wrote: > > > > O

Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit

2018-06-13 Thread Daniel P . Berrangé
On Wed, Jun 13, 2018 at 12:09:59PM -0400, Konrad Rzeszutek Wilk wrote: > On Wed, Jun 13, 2018 at 11:19:49AM +0100, Daniel P. Berrangé wrote: > > On Mon, Jun 04, 2018 at 04:22:05PM -0400, Konrad Rzeszutek Wilk wrote: > > > On Mon, Jun 04, 2018 at 05:07:01PM -0300, Eduardo Habkost wrote: > > > > On F

Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit

2018-06-13 Thread Konrad Rzeszutek Wilk
On Wed, Jun 13, 2018 at 11:19:49AM +0100, Daniel P. Berrangé wrote: > On Mon, Jun 04, 2018 at 04:22:05PM -0400, Konrad Rzeszutek Wilk wrote: > > On Mon, Jun 04, 2018 at 05:07:01PM -0300, Eduardo Habkost wrote: > > > On Fri, Jun 01, 2018 at 11:38:08AM -0400, Konrad Rzeszutek Wilk wrote: > > > > AMD

Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit

2018-06-13 Thread Daniel P . Berrangé
On Mon, Jun 04, 2018 at 04:22:05PM -0400, Konrad Rzeszutek Wilk wrote: > On Mon, Jun 04, 2018 at 05:07:01PM -0300, Eduardo Habkost wrote: > > On Fri, Jun 01, 2018 at 11:38:08AM -0400, Konrad Rzeszutek Wilk wrote: > > > AMD future CPUs expose _two_ ways to utilize the Intel equivalant > > > of the S

Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit

2018-06-08 Thread Tom Lendacky
On 6/6/2018 9:20 AM, Daniel P. Berrangé wrote: > On Tue, Jun 05, 2018 at 08:31:41AM -0500, Tom Lendacky wrote: >> On 6/4/2018 3:07 PM, Eduardo Habkost wrote: >>> On Fri, Jun 01, 2018 at 11:38:08AM -0400, Konrad Rzeszutek Wilk wrote: AMD future CPUs expose _two_ ways to utilize the Intel equiva

Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit

2018-06-06 Thread Daniel P . Berrangé
On Tue, Jun 05, 2018 at 08:31:41AM -0500, Tom Lendacky wrote: > On 6/4/2018 3:07 PM, Eduardo Habkost wrote: > > On Fri, Jun 01, 2018 at 11:38:08AM -0400, Konrad Rzeszutek Wilk wrote: > >> AMD future CPUs expose _two_ ways to utilize the Intel equivalant > >> of the Speculative Store Bypass Disable.

Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit

2018-06-05 Thread Konrad Rzeszutek Wilk
On Mon, Jun 04, 2018 at 06:15:09PM -0300, Eduardo Habkost wrote: > On Mon, Jun 04, 2018 at 04:22:05PM -0400, Konrad Rzeszutek Wilk wrote: > > On Mon, Jun 04, 2018 at 05:07:01PM -0300, Eduardo Habkost wrote: > > > On Fri, Jun 01, 2018 at 11:38:08AM -0400, Konrad Rzeszutek Wilk wrote: > > > > AMD fut

Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit

2018-06-05 Thread Daniel P . Berrangé
On Tue, Jun 05, 2018 at 08:31:41AM -0500, Tom Lendacky wrote: > On 6/4/2018 3:07 PM, Eduardo Habkost wrote: > > On Fri, Jun 01, 2018 at 11:38:08AM -0400, Konrad Rzeszutek Wilk wrote: > >> AMD future CPUs expose _two_ ways to utilize the Intel equivalant > >> of the Speculative Store Bypass Disable.

Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit

2018-06-05 Thread Tom Lendacky
On 6/4/2018 3:07 PM, Eduardo Habkost wrote: > On Fri, Jun 01, 2018 at 11:38:08AM -0400, Konrad Rzeszutek Wilk wrote: >> AMD future CPUs expose _two_ ways to utilize the Intel equivalant >> of the Speculative Store Bypass Disable. The first is via >> the virtualized VIRT_SPEC CTRL MSR (0xC001_011f)

Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit

2018-06-04 Thread Eduardo Habkost
On Mon, Jun 04, 2018 at 04:22:05PM -0400, Konrad Rzeszutek Wilk wrote: > On Mon, Jun 04, 2018 at 05:07:01PM -0300, Eduardo Habkost wrote: > > On Fri, Jun 01, 2018 at 11:38:08AM -0400, Konrad Rzeszutek Wilk wrote: > > > AMD future CPUs expose _two_ ways to utilize the Intel equivalant > > > of the S

Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit

2018-06-04 Thread Konrad Rzeszutek Wilk
On Mon, Jun 04, 2018 at 05:07:01PM -0300, Eduardo Habkost wrote: > On Fri, Jun 01, 2018 at 11:38:08AM -0400, Konrad Rzeszutek Wilk wrote: > > AMD future CPUs expose _two_ ways to utilize the Intel equivalant > > of the Speculative Store Bypass Disable. The first is via > > the virtualized VIRT_SPEC

Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit

2018-06-04 Thread Konrad Rzeszutek Wilk
On Mon, Jun 04, 2018 at 09:54:40AM +0100, Daniel P. Berrangé wrote: > On Fri, Jun 01, 2018 at 11:38:08AM -0400, Konrad Rzeszutek Wilk wrote: > > AMD future CPUs expose _two_ ways to utilize the Intel equivalant > > of the Speculative Store Bypass Disable. The first is via > > the virtualized VIRT_S

Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit

2018-06-04 Thread Eduardo Habkost
On Fri, Jun 01, 2018 at 11:38:08AM -0400, Konrad Rzeszutek Wilk wrote: > AMD future CPUs expose _two_ ways to utilize the Intel equivalant > of the Speculative Store Bypass Disable. The first is via > the virtualized VIRT_SPEC CTRL MSR (0xC001_011f) and the second > is via the SPEC_CTRL MSR (0x48).

Re: [Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit

2018-06-04 Thread Daniel P . Berrangé
On Fri, Jun 01, 2018 at 11:38:08AM -0400, Konrad Rzeszutek Wilk wrote: > AMD future CPUs expose _two_ ways to utilize the Intel equivalant > of the Speculative Store Bypass Disable. The first is via > the virtualized VIRT_SPEC CTRL MSR (0xC001_011f) and the second > is via the SPEC_CTRL MSR (0x48).

[Qemu-devel] [PATCH 1/2] i386: define the AMD 'amd-ssbd' CPUID feature bit

2018-06-01 Thread Konrad Rzeszutek Wilk
AMD future CPUs expose _two_ ways to utilize the Intel equivalant of the Speculative Store Bypass Disable. The first is via the virtualized VIRT_SPEC CTRL MSR (0xC001_011f) and the second is via the SPEC_CTRL MSR (0x48). The document titled: 124441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_fin