Re: [Qemu-devel] [PATCH 1/3] ppc: fix MSR_ME handling for system reset interrupt

2016-10-20 Thread Nicholas Piggin
On Fri, 21 Oct 2016 12:09:15 +1100 David Gibson wrote: > On Thu, Oct 20, 2016 at 05:59:10PM +1100, Nicholas Piggin wrote: > > Power ISA specifies ME bit handling for system reset interrupt: > > > > if the interrupt occurred while the thread was in power-saving > > mode, set to 1; otherwi

Re: [Qemu-devel] [PATCH 1/3] ppc: fix MSR_ME handling for system reset interrupt

2016-10-20 Thread David Gibson
On Thu, Oct 20, 2016 at 05:59:10PM +1100, Nicholas Piggin wrote: > Power ISA specifies ME bit handling for system reset interrupt: > > if the interrupt occurred while the thread was in power-saving > mode, set to 1; otherwise not altered > > Signed-off-by: Nicholas Piggin I've applied t

[Qemu-devel] [PATCH 1/3] ppc: fix MSR_ME handling for system reset interrupt

2016-10-20 Thread Nicholas Piggin
Power ISA specifies ME bit handling for system reset interrupt: if the interrupt occurred while the thread was in power-saving mode, set to 1; otherwise not altered Signed-off-by: Nicholas Piggin --- target-ppc/excp_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) dif