[Qemu-devel] [PATCH 1/4] Implement address masking for SPARC v9 CPUs

2012-05-12 Thread Artyom Tarasenko
According to UltraSPARC - IIi User's manual: 14.1.11 Address Masking (Impdep #125) When PSTATE.AM=1, the CALL, JMPL, and RDPC instructions and all traps transmit zero in the high-order 32-bits of the PC to their specified destination registers. Signed-off-by: Artyom Tarasenko atar4q...@gmail.com

Re: [Qemu-devel] [PATCH 1/4] Implement address masking for SPARC v9 CPUs

2012-05-12 Thread Artyom Tarasenko
Ups, the subject line was supposed to be [PATCH 1/4, master+QEMU 1.1] ... Should I resend? On Sat, May 12, 2012 at 11:15 AM, Artyom Tarasenko atar4q...@gmail.com wrote: According to UltraSPARC - IIi User's manual: 14.1.11 Address Masking (Impdep #125) When PSTATE.AM=1, the CALL, JMPL, and