On Fri, Jul 24, 2015 at 11:06:01AM +0100, Peter Maydell wrote:
> On 24 July 2015 at 10:48, Edgar E. Iglesias wrote:
> > On Thu, Jul 16, 2015 at 12:47:26PM +0100, Peter Maydell wrote:
> >> +{ .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64,
> >> + .opc0 = 3, .opc1 = 7, .crn = 14, .crm
On 24 July 2015 at 10:48, Edgar E. Iglesias wrote:
> On Thu, Jul 16, 2015 at 12:47:26PM +0100, Peter Maydell wrote:
>> +{ .name = "CNTPS_CVAL_EL1", .state = ARM_CP_STATE_AA64,
>> + .opc0 = 3, .opc1 = 7, .crn = 14, .crm = 2, .opc2 = 2,
>> + .type = ARM_CP_IO,
>> + .accessfn = gt_
On Thu, Jul 16, 2015 at 12:47:26PM +0100, Peter Maydell wrote:
> On CPUs with EL3, there are two physical timers, one for Secure and one
> for Non-secure. Implement this extra timer and the AArch64 registers
> which access it.
>
> Signed-off-by: Peter Maydell
> ---
> target-arm/cpu-qom.h | 1 +
On CPUs with EL3, there are two physical timers, one for Secure and one
for Non-secure. Implement this extra timer and the AArch64 registers
which access it.
Signed-off-by: Peter Maydell
---
target-arm/cpu-qom.h | 1 +
target-arm/cpu.c | 2 ++
target-arm/cpu.h | 3 +-
target-arm/helpe
