Re: [Qemu-devel] [PATCH 1/7] target-ppc: kvm: fix floating point registers sync on little-endian hosts

2016-01-19 Thread Greg Kurz
On Tue, 19 Jan 2016 11:55:10 +1100 David Gibson wrote: > On Mon, Jan 18, 2016 at 09:51:56AM +0100, Greg Kurz wrote: > > On Mon, 18 Jan 2016 13:16:44 +1100 > > David Gibson wrote: > > > > > On Fri, Jan 15, 2016 at 04:00:12PM +0100,

Re: [Qemu-devel] [PATCH 1/7] target-ppc: kvm: fix floating point registers sync on little-endian hosts

2016-01-18 Thread Greg Kurz
On Mon, 18 Jan 2016 13:16:44 +1100 David Gibson wrote: > On Fri, Jan 15, 2016 at 04:00:12PM +0100, Greg Kurz wrote: > > On VSX capable CPUs, the 32 FP registers are mapped to the high-bits > > of the 32 first VSX registers. So if you have: > > > > VSR31 = (uint128)

Re: [Qemu-devel] [PATCH 1/7] target-ppc: kvm: fix floating point registers sync on little-endian hosts

2016-01-18 Thread David Gibson
On Mon, Jan 18, 2016 at 09:51:56AM +0100, Greg Kurz wrote: > On Mon, 18 Jan 2016 13:16:44 +1100 > David Gibson wrote: > > > On Fri, Jan 15, 2016 at 04:00:12PM +0100, Greg Kurz wrote: > > > On VSX capable CPUs, the 32 FP registers are mapped to the high-bits > > > of

Re: [Qemu-devel] [PATCH 1/7] target-ppc: kvm: fix floating point registers sync on little-endian hosts

2016-01-17 Thread David Gibson
On Fri, Jan 15, 2016 at 04:00:12PM +0100, Greg Kurz wrote: > On VSX capable CPUs, the 32 FP registers are mapped to the high-bits > of the 32 first VSX registers. So if you have: > > VSR31 = (uint128) 0x0102030405060708090a0b0c0d0e0f00 > > then > > FPR31 = (uint64) 0x0102030405060708 > > The

[Qemu-devel] [PATCH 1/7] target-ppc: kvm: fix floating point registers sync on little-endian hosts

2016-01-15 Thread Greg Kurz
On VSX capable CPUs, the 32 FP registers are mapped to the high-bits of the 32 first VSX registers. So if you have: VSR31 = (uint128) 0x0102030405060708090a0b0c0d0e0f00 then FPR31 = (uint64) 0x0102030405060708 The kernel stores the VSX registers in the fp_state struct following the host endian

[Qemu-devel] [PATCH 1/7] target-ppc: kvm: fix floating point registers sync on little-endian hosts

2015-12-18 Thread Greg Kurz
On VSX capable CPUs, the 32 FP registers are mapped to the high-bits of the 32 first VSX registers. So if you have: VSR31 = (uint128) 0x0102030405060708090a0b0c0d0e0f00 then FPR31 = (uint64) 0x0102030405060708 The kernel stores the VSX registers in the fp_state struct following the host endian