On 21/06/2016 15:46, Ефимов Василий wrote:
>> I've sent a patch series for you to rebase patch 10 and 11 on. Let me
>> know what you think!
> I see no problems with the patch series. In second version, I'll create
> named GPIO ("gsi") for the new IRQ vector gsi (patch 10). The vector
> will be u
20.06.2016 17:40, Paolo Bonzini wrote:
I've sent a patch series for you to rebase patch 10 and 11 on. Let me
know what you think!
I see no problems with the patch series. In second version, I'll create
named GPIO ("gsi") for the new IRQ vector gsi (patch 10). The vector
will be used to set up
On 17/06/2016 16:03, Paolo Bonzini wrote:
> The modeling here was weird. ICH9 does not need both ->pic and
> ->ioapic, it can make do with just a 24-entry GSI array.
>
> If you change that in the previous patch, this one makes much more
> sense. As it is now, it seems like the ISA bus will not
On 17/06/2016 15:11, Efimov Vasily wrote:
> The isa_bus_irqs function initializes ISA bus IRQ array pointer with specified
> value.
>
> Previously the ICH9 LPC bridge model did not have its own IRQs but
> only IRQ pointer cache. And same GSI were used for ISA bus and other sources
> behind the b
The isa_bus_irqs function initializes ISA bus IRQ array pointer with specified
value.
Previously the ICH9 LPC bridge model did not have its own IRQs but
only IRQ pointer cache. And same GSI were used for ISA bus and other sources
behind the bridge (PCI, SCI). Hence, the pc_q35_init was only possib
