Add an explicit CPUPPCState parameter instead of relying on AREG0. Signed-off-by: Blue Swirl <blauwir...@gmail.com> --- Makefile.target | 3 -- target-ppc/helper.h | 74 +++++++++++++++++------------------ target-ppc/mmu_helper.c | 91 ++++++++++++++++++++++--------------------- target-ppc/translate.c | 85 +++++++++++++++++++++------------------- target-ppc/translate_init.c | 24 ++++++------ 5 files changed, 142 insertions(+), 135 deletions(-)
diff --git a/Makefile.target b/Makefile.target index 87b3f53..92c90ae 100644 --- a/Makefile.target +++ b/Makefile.target @@ -123,9 +123,6 @@ ifneq ($(TARGET_BASE_ARCH), sparc) op_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS) endif user-exec.o: QEMU_CFLAGS += $(HELPER_CFLAGS) -ifeq ($(TARGET_BASE_ARCH), ppc) -mmu_helper.o: QEMU_CFLAGS += $(HELPER_CFLAGS) -endif # Note: this is a workaround. The real fix is to avoid compiling # cpu_signal_handler() in user-exec.c. diff --git a/target-ppc/helper.h b/target-ppc/helper.h index 7074bad..b1f7ba5 100644 --- a/target-ppc/helper.h +++ b/target-ppc/helper.h @@ -324,38 +324,38 @@ DEF_HELPER_3(efdcmpgt, i32, env, i64, i64) DEF_HELPER_3(efdcmpeq, i32, env, i64, i64) #if !defined(CONFIG_USER_ONLY) -DEF_HELPER_1(4xx_tlbre_hi, tl, tl) -DEF_HELPER_1(4xx_tlbre_lo, tl, tl) -DEF_HELPER_2(4xx_tlbwe_hi, void, tl, tl) -DEF_HELPER_2(4xx_tlbwe_lo, void, tl, tl) -DEF_HELPER_1(4xx_tlbsx, tl, tl) -DEF_HELPER_2(440_tlbre, tl, i32, tl) -DEF_HELPER_3(440_tlbwe, void, i32, tl, tl) -DEF_HELPER_1(440_tlbsx, tl, tl) -DEF_HELPER_0(booke206_tlbre, void) -DEF_HELPER_0(booke206_tlbwe, void) -DEF_HELPER_1(booke206_tlbsx, void, tl) -DEF_HELPER_1(booke206_tlbivax, void, tl) -DEF_HELPER_1(booke206_tlbilx0, void, tl) -DEF_HELPER_1(booke206_tlbilx1, void, tl) -DEF_HELPER_1(booke206_tlbilx3, void, tl) -DEF_HELPER_1(booke206_tlbflush, void, i32) -DEF_HELPER_2(booke_setpid, void, i32, tl) -DEF_HELPER_1(6xx_tlbd, void, tl) -DEF_HELPER_1(6xx_tlbi, void, tl) -DEF_HELPER_1(74xx_tlbd, void, tl) -DEF_HELPER_1(74xx_tlbi, void, tl) -DEF_HELPER_FLAGS_0(tlbia, TCG_CALL_CONST, void) -DEF_HELPER_FLAGS_1(tlbie, TCG_CALL_CONST, void, tl) +DEF_HELPER_2(4xx_tlbre_hi, tl, env, tl) +DEF_HELPER_2(4xx_tlbre_lo, tl, env, tl) +DEF_HELPER_3(4xx_tlbwe_hi, void, env, tl, tl) +DEF_HELPER_3(4xx_tlbwe_lo, void, env, tl, tl) +DEF_HELPER_2(4xx_tlbsx, tl, env, tl) +DEF_HELPER_3(440_tlbre, tl, env, i32, tl) +DEF_HELPER_4(440_tlbwe, void, env, i32, tl, tl) +DEF_HELPER_2(440_tlbsx, tl, env, tl) +DEF_HELPER_1(booke206_tlbre, void, env) +DEF_HELPER_1(booke206_tlbwe, void, env) +DEF_HELPER_2(booke206_tlbsx, void, env, tl) +DEF_HELPER_2(booke206_tlbivax, void, env, tl) +DEF_HELPER_2(booke206_tlbilx0, void, env, tl) +DEF_HELPER_2(booke206_tlbilx1, void, env, tl) +DEF_HELPER_2(booke206_tlbilx3, void, env, tl) +DEF_HELPER_2(booke206_tlbflush, void, env, i32) +DEF_HELPER_3(booke_setpid, void, env, i32, tl) +DEF_HELPER_2(6xx_tlbd, void, env, tl) +DEF_HELPER_2(6xx_tlbi, void, env, tl) +DEF_HELPER_2(74xx_tlbd, void, env, tl) +DEF_HELPER_2(74xx_tlbi, void, env, tl) +DEF_HELPER_FLAGS_1(tlbia, TCG_CALL_CONST, void, env) +DEF_HELPER_FLAGS_2(tlbie, TCG_CALL_CONST, void, env, tl) #if defined(TARGET_PPC64) -DEF_HELPER_FLAGS_2(store_slb, TCG_CALL_CONST, void, tl, tl) -DEF_HELPER_1(load_slb_esid, tl, tl) -DEF_HELPER_1(load_slb_vsid, tl, tl) -DEF_HELPER_FLAGS_0(slbia, TCG_CALL_CONST, void) -DEF_HELPER_FLAGS_1(slbie, TCG_CALL_CONST, void, tl) +DEF_HELPER_FLAGS_3(store_slb, TCG_CALL_CONST, void, env, tl, tl) +DEF_HELPER_2(load_slb_esid, tl, env, tl) +DEF_HELPER_2(load_slb_vsid, tl, env, tl) +DEF_HELPER_FLAGS_1(slbia, TCG_CALL_CONST, void, env) +DEF_HELPER_FLAGS_2(slbie, TCG_CALL_CONST, void, env, tl) #endif -DEF_HELPER_FLAGS_1(load_sr, TCG_CALL_CONST, tl, tl); -DEF_HELPER_FLAGS_2(store_sr, TCG_CALL_CONST, void, tl, tl) +DEF_HELPER_FLAGS_2(load_sr, TCG_CALL_CONST, tl, env, tl); +DEF_HELPER_FLAGS_3(store_sr, TCG_CALL_CONST, void, env, tl, tl) DEF_HELPER_FLAGS_1(602_mfrom, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl) DEF_HELPER_1(msgsnd, void, tl) @@ -365,7 +365,7 @@ DEF_HELPER_2(msgclr, void, env, tl) DEF_HELPER_4(dlmzb, tl, env, tl, tl, i32) DEF_HELPER_FLAGS_1(clcs, TCG_CALL_CONST | TCG_CALL_PURE, tl, i32) #if !defined(CONFIG_USER_ONLY) -DEF_HELPER_1(rac, tl, tl) +DEF_HELPER_2(rac, tl, env, tl) #endif DEF_HELPER_3(div, tl, env, tl, tl) DEF_HELPER_3(divo, tl, env, tl, tl) @@ -405,12 +405,12 @@ DEF_HELPER_1(store_40x_dbcr0, void, tl) DEF_HELPER_1(store_40x_sler, void, tl) DEF_HELPER_1(store_booke_tcr, void, tl) DEF_HELPER_1(store_booke_tsr, void, tl) -DEF_HELPER_2(store_ibatl, void, i32, tl) -DEF_HELPER_2(store_ibatu, void, i32, tl) -DEF_HELPER_2(store_dbatl, void, i32, tl) -DEF_HELPER_2(store_dbatu, void, i32, tl) -DEF_HELPER_2(store_601_batl, void, i32, tl) -DEF_HELPER_2(store_601_batu, void, i32, tl) +DEF_HELPER_3(store_ibatl, void, env, i32, tl) +DEF_HELPER_3(store_ibatu, void, env, i32, tl) +DEF_HELPER_3(store_dbatl, void, env, i32, tl) +DEF_HELPER_3(store_dbatu, void, env, i32, tl) +DEF_HELPER_3(store_601_batl, void, env, i32, tl) +DEF_HELPER_3(store_601_batu, void, env, i32, tl) #endif #include "def-helper.h" diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 81800b6..7bd6230 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -17,7 +17,6 @@ * License along with this library; if not, see <http://www.gnu.org/licenses/>. */ #include "cpu.h" -#include "dyngen-exec.h" #include "helper.h" //#define DEBUG_SOFTWARE_TLB @@ -32,38 +31,38 @@ /* SPR accesses */ #if !defined(CONFIG_USER_ONLY) -void helper_store_ibatu(uint32_t nr, target_ulong val) +void helper_store_ibatu(CPUPPCState *env, uint32_t nr, target_ulong val) { ppc_store_ibatu(env, nr, val); } -void helper_store_ibatl(uint32_t nr, target_ulong val) +void helper_store_ibatl(CPUPPCState *env, uint32_t nr, target_ulong val) { ppc_store_ibatl(env, nr, val); } -void helper_store_dbatu(uint32_t nr, target_ulong val) +void helper_store_dbatu(CPUPPCState *env, uint32_t nr, target_ulong val) { ppc_store_dbatu(env, nr, val); } -void helper_store_dbatl(uint32_t nr, target_ulong val) +void helper_store_dbatl(CPUPPCState *env, uint32_t nr, target_ulong val) { ppc_store_dbatl(env, nr, val); } -void helper_store_601_batl(uint32_t nr, target_ulong val) +void helper_store_601_batl(CPUPPCState *env, uint32_t nr, target_ulong val) { ppc_store_ibatl_601(env, nr, val); } -void helper_store_601_batu(uint32_t nr, target_ulong val) +void helper_store_601_batu(CPUPPCState *env, uint32_t nr, target_ulong val) { ppc_store_ibatu_601(env, nr, val); } /* Segment registers load and store */ -target_ulong helper_load_sr(target_ulong sr_num) +target_ulong helper_load_sr(CPUPPCState *env, target_ulong sr_num) { #if defined(TARGET_PPC64) if (env->mmu_model & POWERPC_MMU_64) { @@ -73,14 +72,14 @@ target_ulong helper_load_sr(target_ulong sr_num) return env->sr[sr_num]; } -void helper_store_sr(target_ulong sr_num, target_ulong val) +void helper_store_sr(CPUPPCState *env, target_ulong sr_num, target_ulong val) { ppc_store_sr(env, sr_num, val); } /* SLB management */ #if defined(TARGET_PPC64) -void helper_store_slb(target_ulong rb, target_ulong rs) +void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs) { if (ppc_store_slb(env, rb, rs) < 0) { helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM, @@ -88,7 +87,7 @@ void helper_store_slb(target_ulong rb, target_ulong rs) } } -target_ulong helper_load_slb_esid(target_ulong rb) +target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb) { target_ulong rt; @@ -99,7 +98,7 @@ target_ulong helper_load_slb_esid(target_ulong rb) return rt; } -target_ulong helper_load_slb_vsid(target_ulong rb) +target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb) { target_ulong rt; @@ -110,12 +109,12 @@ target_ulong helper_load_slb_vsid(target_ulong rb) return rt; } -void helper_slbia(void) +void helper_slbia(CPUPPCState *env) { ppc_slb_invalidate_all(env); } -void helper_slbie(target_ulong addr) +void helper_slbie(CPUPPCState *env, target_ulong addr) { ppc_slb_invalidate_one(env, addr); } @@ -123,19 +122,19 @@ void helper_slbie(target_ulong addr) #endif /* defined(TARGET_PPC64) */ /* TLB management */ -void helper_tlbia(void) +void helper_tlbia(CPUPPCState *env) { ppc_tlb_invalidate_all(env); } -void helper_tlbie(target_ulong addr) +void helper_tlbie(CPUPPCState *env, target_ulong addr) { ppc_tlb_invalidate_one(env, addr); } /* Software driven TLBs management */ /* PowerPC 602/603 software TLB load instructions helpers */ -static void do_6xx_tlb(target_ulong new_EPN, int is_code) +static void do_6xx_tlb(CPUPPCState *env, target_ulong new_EPN, int is_code) { target_ulong RPN, CMP, EPN; int way; @@ -158,18 +157,18 @@ static void do_6xx_tlb(target_ulong new_EPN, int is_code) way, is_code, CMP, RPN); } -void helper_6xx_tlbd(target_ulong EPN) +void helper_6xx_tlbd(CPUPPCState *env, target_ulong EPN) { - do_6xx_tlb(EPN, 0); + do_6xx_tlb(env, EPN, 0); } -void helper_6xx_tlbi(target_ulong EPN) +void helper_6xx_tlbi(CPUPPCState *env, target_ulong EPN) { - do_6xx_tlb(EPN, 1); + do_6xx_tlb(env, EPN, 1); } /* PowerPC 74xx software TLB load instructions helpers */ -static void do_74xx_tlb(target_ulong new_EPN, int is_code) +static void do_74xx_tlb(CPUPPCState *env, target_ulong new_EPN, int is_code) { target_ulong RPN, CMP, EPN; int way; @@ -187,20 +186,20 @@ static void do_74xx_tlb(target_ulong new_EPN, int is_code) way, is_code, CMP, RPN); } -void helper_74xx_tlbd(target_ulong EPN) +void helper_74xx_tlbd(CPUPPCState *env, target_ulong EPN) { - do_74xx_tlb(EPN, 0); + do_74xx_tlb(env, EPN, 0); } -void helper_74xx_tlbi(target_ulong EPN) +void helper_74xx_tlbi(CPUPPCState *env, target_ulong EPN) { - do_74xx_tlb(EPN, 1); + do_74xx_tlb(env, EPN, 1); } /*****************************************************************************/ /* PowerPC 601 specific instructions (POWER bridge) */ -target_ulong helper_rac(target_ulong addr) +target_ulong helper_rac(CPUPPCState *env, target_ulong addr) { mmu_ctx_t ctx; int nb_BATs; @@ -303,7 +302,7 @@ static inline int booke_page_size_to_tlb(target_ulong page_size) #define PPC4XX_TLBLO_ATTR_MASK 0x000000FF #define PPC4XX_TLBLO_RPN_MASK 0xFFFFFC00 -target_ulong helper_4xx_tlbre_hi(target_ulong entry) +target_ulong helper_4xx_tlbre_hi(CPUPPCState *env, target_ulong entry) { ppcemb_tlb_t *tlb; target_ulong ret; @@ -324,7 +323,7 @@ target_ulong helper_4xx_tlbre_hi(target_ulong entry) return ret; } -target_ulong helper_4xx_tlbre_lo(target_ulong entry) +target_ulong helper_4xx_tlbre_lo(CPUPPCState *env, target_ulong entry) { ppcemb_tlb_t *tlb; target_ulong ret; @@ -341,7 +340,8 @@ target_ulong helper_4xx_tlbre_lo(target_ulong entry) return ret; } -void helper_4xx_tlbwe_hi(target_ulong entry, target_ulong val) +void helper_4xx_tlbwe_hi(CPUPPCState *env, target_ulong entry, + target_ulong val) { ppcemb_tlb_t *tlb; target_ulong page, end; @@ -400,7 +400,8 @@ void helper_4xx_tlbwe_hi(target_ulong entry, target_ulong val) } } -void helper_4xx_tlbwe_lo(target_ulong entry, target_ulong val) +void helper_4xx_tlbwe_lo(CPUPPCState *env, target_ulong entry, + target_ulong val) { ppcemb_tlb_t *tlb; @@ -426,13 +427,14 @@ void helper_4xx_tlbwe_lo(target_ulong entry, target_ulong val) tlb->prot & PAGE_VALID ? 'v' : '-', (int)tlb->PID); } -target_ulong helper_4xx_tlbsx(target_ulong address) +target_ulong helper_4xx_tlbsx(CPUPPCState *env, target_ulong address) { return ppcemb_tlb_search(env, address, env->spr[SPR_40x_PID]); } /* PowerPC 440 TLB management */ -void helper_440_tlbwe(uint32_t word, target_ulong entry, target_ulong value) +void helper_440_tlbwe(CPUPPCState *env, uint32_t word, target_ulong entry, + target_ulong value) { ppcemb_tlb_t *tlb; target_ulong EPN, RPN, size; @@ -504,7 +506,8 @@ void helper_440_tlbwe(uint32_t word, target_ulong entry, target_ulong value) } } -target_ulong helper_440_tlbre(uint32_t word, target_ulong entry) +target_ulong helper_440_tlbre(CPUPPCState *env, uint32_t word, + target_ulong entry) { ppcemb_tlb_t *tlb; target_ulong ret; @@ -559,7 +562,7 @@ target_ulong helper_440_tlbre(uint32_t word, target_ulong entry) return ret; } -target_ulong helper_440_tlbsx(target_ulong address) +target_ulong helper_440_tlbsx(CPUPPCState *env, target_ulong address) { return ppcemb_tlb_search(env, address, env->spr[SPR_440_MMUCR] & 0xFF); } @@ -583,14 +586,14 @@ static ppcmas_tlb_t *booke206_cur_tlb(CPUPPCState *env) return booke206_get_tlbm(env, tlb, ea, esel); } -void helper_booke_setpid(uint32_t pidn, target_ulong pid) +void helper_booke_setpid(CPUPPCState *env, uint32_t pidn, target_ulong pid) { env->spr[pidn] = pid; /* changing PIDs mean we're in a different address space now */ tlb_flush(env, 1); } -void helper_booke206_tlbwe(void) +void helper_booke206_tlbwe(CPUPPCState *env) { uint32_t tlbncfg, tlbn; ppcmas_tlb_t *tlb; @@ -687,7 +690,7 @@ static inline void booke206_tlb_to_mas(CPUPPCState *env, ppcmas_tlb_t *tlb) env->spr[SPR_BOOKE_MAS7] = tlb->mas7_3 >> 32; } -void helper_booke206_tlbre(void) +void helper_booke206_tlbre(CPUPPCState *env) { ppcmas_tlb_t *tlb = NULL; @@ -699,7 +702,7 @@ void helper_booke206_tlbre(void) } } -void helper_booke206_tlbsx(target_ulong address) +void helper_booke206_tlbsx(CPUPPCState *env, target_ulong address) { ppcmas_tlb_t *tlb = NULL; int i, j; @@ -773,7 +776,7 @@ static inline void booke206_invalidate_ea_tlb(CPUPPCState *env, int tlbn, } } -void helper_booke206_tlbivax(target_ulong address) +void helper_booke206_tlbivax(CPUPPCState *env, target_ulong address) { if (address & 0x4) { /* flush all entries */ @@ -798,13 +801,13 @@ void helper_booke206_tlbivax(target_ulong address) } } -void helper_booke206_tlbilx0(target_ulong address) +void helper_booke206_tlbilx0(CPUPPCState *env, target_ulong address) { /* XXX missing LPID handling */ booke206_flush_tlb(env, -1, 1); } -void helper_booke206_tlbilx1(target_ulong address) +void helper_booke206_tlbilx1(CPUPPCState *env, target_ulong address) { int i, j; int tid = (env->spr[SPR_BOOKE_MAS6] & MAS6_SPID); @@ -825,7 +828,7 @@ void helper_booke206_tlbilx1(target_ulong address) tlb_flush(env, 1); } -void helper_booke206_tlbilx3(target_ulong address) +void helper_booke206_tlbilx3(CPUPPCState *env, target_ulong address) { int i, j; ppcmas_tlb_t *tlb; @@ -865,7 +868,7 @@ void helper_booke206_tlbilx3(target_ulong address) tlb_flush(env, 1); } -void helper_booke206_tlbflush(uint32_t type) +void helper_booke206_tlbflush(CPUPPCState *env, uint32_t type) { int flags = 0; diff --git a/target-ppc/translate.c b/target-ppc/translate.c index eb3cd5a..446f97e 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -4200,7 +4200,7 @@ static void gen_mfsr(DisasContext *ctx) return; } t0 = tcg_const_tl(SR(ctx->opcode)); - gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); + gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); tcg_temp_free(t0); #endif } @@ -4219,7 +4219,7 @@ static void gen_mfsrin(DisasContext *ctx) t0 = tcg_temp_new(); tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); tcg_gen_andi_tl(t0, t0, 0xF); - gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); + gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); tcg_temp_free(t0); #endif } @@ -4236,7 +4236,7 @@ static void gen_mtsr(DisasContext *ctx) return; } t0 = tcg_const_tl(SR(ctx->opcode)); - gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]); + gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); tcg_temp_free(t0); #endif } @@ -4255,7 +4255,7 @@ static void gen_mtsrin(DisasContext *ctx) t0 = tcg_temp_new(); tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); tcg_gen_andi_tl(t0, t0, 0xF); - gen_helper_store_sr(t0, cpu_gpr[rD(ctx->opcode)]); + gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]); tcg_temp_free(t0); #endif } @@ -4275,7 +4275,7 @@ static void gen_mfsr_64b(DisasContext *ctx) return; } t0 = tcg_const_tl(SR(ctx->opcode)); - gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); + gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); tcg_temp_free(t0); #endif } @@ -4294,7 +4294,7 @@ static void gen_mfsrin_64b(DisasContext *ctx) t0 = tcg_temp_new(); tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); tcg_gen_andi_tl(t0, t0, 0xF); - gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], t0); + gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); tcg_temp_free(t0); #endif } @@ -4311,7 +4311,7 @@ static void gen_mtsr_64b(DisasContext *ctx) return; } t0 = tcg_const_tl(SR(ctx->opcode)); - gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]); + gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); tcg_temp_free(t0); #endif } @@ -4330,7 +4330,7 @@ static void gen_mtsrin_64b(DisasContext *ctx) t0 = tcg_temp_new(); tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28); tcg_gen_andi_tl(t0, t0, 0xF); - gen_helper_store_sr(t0, cpu_gpr[rS(ctx->opcode)]); + gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]); tcg_temp_free(t0); #endif } @@ -4345,7 +4345,8 @@ static void gen_slbmte(DisasContext *ctx) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); return; } - gen_helper_store_slb(cpu_gpr[rB(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); + gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)], + cpu_gpr[rS(ctx->opcode)]); #endif } @@ -4358,7 +4359,7 @@ static void gen_slbmfee(DisasContext *ctx) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); return; } - gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], + gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env, cpu_gpr[rB(ctx->opcode)]); #endif } @@ -4372,7 +4373,7 @@ static void gen_slbmfev(DisasContext *ctx) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); return; } - gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], + gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env, cpu_gpr[rB(ctx->opcode)]); #endif } @@ -4391,7 +4392,7 @@ static void gen_tlbia(DisasContext *ctx) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; } - gen_helper_tlbia(); + gen_helper_tlbia(cpu_env); #endif } @@ -4405,7 +4406,7 @@ static void gen_tlbiel(DisasContext *ctx) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; } - gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]); + gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); #endif } @@ -4423,11 +4424,11 @@ static void gen_tlbie(DisasContext *ctx) if (!ctx->sf_mode) { TCGv t0 = tcg_temp_new(); tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); - gen_helper_tlbie(t0); + gen_helper_tlbie(cpu_env, t0); tcg_temp_free(t0); } else #endif - gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]); + gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); #endif } @@ -4459,7 +4460,7 @@ static void gen_slbia(DisasContext *ctx) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; } - gen_helper_slbia(); + gen_helper_slbia(cpu_env); #endif } @@ -4473,7 +4474,7 @@ static void gen_slbie(DisasContext *ctx) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; } - gen_helper_slbie(cpu_gpr[rB(ctx->opcode)]); + gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); #endif } #endif @@ -5194,7 +5195,7 @@ static void gen_tlbld_6xx(DisasContext *ctx) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; } - gen_helper_6xx_tlbd(cpu_gpr[rB(ctx->opcode)]); + gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); #endif } @@ -5208,7 +5209,7 @@ static void gen_tlbli_6xx(DisasContext *ctx) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; } - gen_helper_6xx_tlbi(cpu_gpr[rB(ctx->opcode)]); + gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); #endif } @@ -5224,7 +5225,7 @@ static void gen_tlbld_74xx(DisasContext *ctx) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; } - gen_helper_74xx_tlbd(cpu_gpr[rB(ctx->opcode)]); + gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]); #endif } @@ -5238,7 +5239,7 @@ static void gen_tlbli_74xx(DisasContext *ctx) gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC); return; } - gen_helper_74xx_tlbi(cpu_gpr[rB(ctx->opcode)]); + gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]); #endif } @@ -5286,7 +5287,7 @@ static void gen_mfsri(DisasContext *ctx) gen_addr_reg_index(ctx, t0); tcg_gen_shri_tl(t0, t0, 28); tcg_gen_andi_tl(t0, t0, 0xF); - gen_helper_load_sr(cpu_gpr[rd], t0); + gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0); tcg_temp_free(t0); if (ra != 0 && ra != rd) tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]); @@ -5305,7 +5306,7 @@ static void gen_rac(DisasContext *ctx) } t0 = tcg_temp_new(); gen_addr_reg_index(ctx, t0); - gen_helper_rac(cpu_gpr[rD(ctx->opcode)], t0); + gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); tcg_temp_free(t0); #endif } @@ -5483,7 +5484,7 @@ static void gen_tlbiva(DisasContext *ctx) } t0 = tcg_temp_new(); gen_addr_reg_index(ctx, t0); - gen_helper_tlbie(cpu_gpr[rB(ctx->opcode)]); + gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]); tcg_temp_free(t0); #endif } @@ -5946,10 +5947,12 @@ static void gen_tlbre_40x(DisasContext *ctx) } switch (rB(ctx->opcode)) { case 0: - gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); + gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env, + cpu_gpr[rA(ctx->opcode)]); break; case 1: - gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); + gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env, + cpu_gpr[rA(ctx->opcode)]); break; default: gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); @@ -5971,7 +5974,7 @@ static void gen_tlbsx_40x(DisasContext *ctx) } t0 = tcg_temp_new(); gen_addr_reg_index(ctx, t0); - gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], t0); + gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); tcg_temp_free(t0); if (Rc(ctx->opcode)) { int l1 = gen_new_label(); @@ -5997,10 +6000,12 @@ static void gen_tlbwe_40x(DisasContext *ctx) } switch (rB(ctx->opcode)) { case 0: - gen_helper_4xx_tlbwe_hi(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); + gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)], + cpu_gpr[rS(ctx->opcode)]); break; case 1: - gen_helper_4xx_tlbwe_lo(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); + gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)], + cpu_gpr[rS(ctx->opcode)]); break; default: gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); @@ -6027,7 +6032,8 @@ static void gen_tlbre_440(DisasContext *ctx) case 2: { TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); - gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], t0, cpu_gpr[rA(ctx->opcode)]); + gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env, + t0, cpu_gpr[rA(ctx->opcode)]); tcg_temp_free_i32(t0); } break; @@ -6051,7 +6057,7 @@ static void gen_tlbsx_440(DisasContext *ctx) } t0 = tcg_temp_new(); gen_addr_reg_index(ctx, t0); - gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], t0); + gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); tcg_temp_free(t0); if (Rc(ctx->opcode)) { int l1 = gen_new_label(); @@ -6081,7 +6087,8 @@ static void gen_tlbwe_440(DisasContext *ctx) case 2: { TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode)); - gen_helper_440_tlbwe(t0, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); + gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)], + cpu_gpr[rS(ctx->opcode)]); tcg_temp_free_i32(t0); } break; @@ -6105,7 +6112,7 @@ static void gen_tlbre_booke206(DisasContext *ctx) return; } - gen_helper_booke206_tlbre(); + gen_helper_booke206_tlbre(cpu_env); #endif } @@ -6129,7 +6136,7 @@ static void gen_tlbsx_booke206(DisasContext *ctx) } tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]); - gen_helper_booke206_tlbsx(t0); + gen_helper_booke206_tlbsx(cpu_env, t0); #endif } @@ -6144,7 +6151,7 @@ static void gen_tlbwe_booke206(DisasContext *ctx) return; } gen_update_nip(ctx, ctx->nip - 4); - gen_helper_booke206_tlbwe(); + gen_helper_booke206_tlbwe(cpu_env); #endif } @@ -6162,7 +6169,7 @@ static void gen_tlbivax_booke206(DisasContext *ctx) t0 = tcg_temp_new(); gen_addr_reg_index(ctx, t0); - gen_helper_booke206_tlbivax(t0); + gen_helper_booke206_tlbivax(cpu_env, t0); #endif } @@ -6182,13 +6189,13 @@ static void gen_tlbilx_booke206(DisasContext *ctx) switch((ctx->opcode >> 21) & 0x3) { case 0: - gen_helper_booke206_tlbilx0(t0); + gen_helper_booke206_tlbilx0(cpu_env, t0); break; case 1: - gen_helper_booke206_tlbilx1(t0); + gen_helper_booke206_tlbilx1(cpu_env, t0); break; case 3: - gen_helper_booke206_tlbilx3(t0); + gen_helper_booke206_tlbilx3(cpu_env, t0); break; default: gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index ba4b84d..bb6d50a 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -279,28 +279,28 @@ static void spr_read_ibat_h (void *opaque, int gprn, int sprn) static void spr_write_ibatu (void *opaque, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); - gen_helper_store_ibatu(t0, cpu_gpr[gprn]); + gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } static void spr_write_ibatu_h (void *opaque, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); - gen_helper_store_ibatu(t0, cpu_gpr[gprn]); + gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } static void spr_write_ibatl (void *opaque, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); - gen_helper_store_ibatl(t0, cpu_gpr[gprn]); + gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } static void spr_write_ibatl_h (void *opaque, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); - gen_helper_store_ibatl(t0, cpu_gpr[gprn]); + gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } @@ -319,28 +319,28 @@ static void spr_read_dbat_h (void *opaque, int gprn, int sprn) static void spr_write_dbatu (void *opaque, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); - gen_helper_store_dbatu(t0, cpu_gpr[gprn]); + gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } static void spr_write_dbatu_h (void *opaque, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); - gen_helper_store_dbatu(t0, cpu_gpr[gprn]); + gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } static void spr_write_dbatl (void *opaque, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); - gen_helper_store_dbatl(t0, cpu_gpr[gprn]); + gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } static void spr_write_dbatl_h (void *opaque, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); - gen_helper_store_dbatl(t0, cpu_gpr[gprn]); + gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } @@ -421,14 +421,14 @@ static void spr_read_601_ubat (void *opaque, int gprn, int sprn) static void spr_write_601_ubatu (void *opaque, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); - gen_helper_store_601_batl(t0, cpu_gpr[gprn]); + gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } static void spr_write_601_ubatl (void *opaque, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); - gen_helper_store_601_batu(t0, cpu_gpr[gprn]); + gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } #endif @@ -1371,14 +1371,14 @@ static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn) static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32(sprn); - gen_helper_booke206_tlbflush(t0); + gen_helper_booke206_tlbflush(cpu_env, t0); tcg_temp_free_i32(t0); } static void spr_write_booke_pid (void *opaque, int sprn, int gprn) { TCGv_i32 t0 = tcg_const_i32(sprn); - gen_helper_booke_setpid(t0, cpu_gpr[gprn]); + gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); tcg_temp_free_i32(t0); } #endif -- 1.7.10
