Re: [Qemu-devel] [PATCH 15/28] target/riscv: Convert quadrant 0 of RVXC insns to decodetree

2018-10-19 Thread Bastian Koppelmann
On 10/13/18 8:18 PM, Richard Henderson wrote: On 10/12/18 10:30 AM, Bastian Koppelmann wrote: +# Argument sets: + rs1 rd +_dw uimm rs1 rd + nzuimm rd + rs1 rs2 +_dw uimm rs1 rs2 I guess this is good enough for now. What I'd like to see is

Re: [Qemu-devel] [PATCH 15/28] target/riscv: Convert quadrant 0 of RVXC insns to decodetree

2018-10-13 Thread Richard Henderson
On 10/12/18 10:30 AM, Bastian Koppelmann wrote: > +# Argument sets: > + rs1 rd > +_dw uimm rs1 rd > + nzuimm rd > + rs1 rs2 > +_dw uimm rs1 rs2 I guess this is good enough for now. What I'd like to see is something like imm rs1 rd

[Qemu-devel] [PATCH 15/28] target/riscv: Convert quadrant 0 of RVXC insns to decodetree

2018-10-12 Thread Bastian Koppelmann
Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/Makefile.objs | 9 ++- target/riscv/insn16.decode | 55 +++ target/riscv/insn_trans/trans_rvc.inc.c | 89 + target/riscv/translate.c| 88