The vector interrupt has higher priority than interrupt_level_n. Also check only interrupt_level_n concurency when TL > 0, the traps of other types may be nested.
Signed-off-by: Artyom Tarasenko <atar4q...@gmail.com> --- hw/sun4u.c | 7 ++++++- 1 files changed, 6 insertions(+), 1 deletions(-) diff --git a/hw/sun4u.c b/hw/sun4u.c index 9d28194..e6b18f7 100644 --- a/hw/sun4u.c +++ b/hw/sun4u.c @@ -254,6 +254,10 @@ void cpu_check_irqs(CPUSPARCState *env) uint32_t pil = env->pil_in | (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER)); + /* TT_IVEC has a higher priority (16) than TT_EXTINT (31..17) */ + if (env->ivec_status & 0x20) { + return; + } /* check if TM or SM in SOFTINT are set setting these also causes interrupt 14 */ if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) { @@ -281,7 +285,8 @@ void cpu_check_irqs(CPUSPARCState *env) int old_interrupt = env->interrupt_index; int new_interrupt = TT_EXTINT | i; - if (env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt) { + if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt + && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) { CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d " "current %x >= pending %x\n", env->tl, cpu_tsptr(env)->tt, new_interrupt); -- 1.7.3.4