Am 08.10.2012 10:50, schrieb Alexander Graf:
>
> On 08.10.2012, at 10:23, Bhushan Bharat-R65777 wrote:
@@ -307,6 +313,16 @@ static const VMStateDescription
vmstate_ppce500_pci = {
#include "exec-memory.h"
+static int e500_pcihost_bridge_initfn(PCIDevice *d) {
+
On 08.10.2012, at 10:23, Bhushan Bharat-R65777 wrote:
>>> Which device's initialization function you are talking about?
>>
>> static const TypeInfo e500_host_bridge_info = {
>> .name = "e500-host-bridge",
>> .parent= TYPE_PCI_DEVICE,
>> .instance_size
> > Which device's initialization function you are talking about?
>
> static const TypeInfo e500_host_bridge_info = {
> .name = "e500-host-bridge",
> .parent= TYPE_PCI_DEVICE,
> .instance_size = sizeof(PCIDevice),
> .class_init= e500_ho
On 10/07/2012 01:57 PM, Alexander Graf wrote:
>
>
> On 07.10.2012, at 11:48, Avi Kivity wrote:
>
>> On 10/05/2012 01:59 PM, Alexander Graf wrote:
>> Do you mean that we add the "MemoryRegion bar0" in PCIDevice struct. Do
>> the
> same thing that I was doing in e500_pcihost_initfn()
On 07.10.2012, at 11:48, Avi Kivity wrote:
> On 10/05/2012 01:59 PM, Alexander Graf wrote:
> Do you mean that we add the "MemoryRegion bar0" in PCIDevice struct. Do
> the
same thing that I was doing in e500_pcihost_initfn() in the k->init()
(will add
this) function of "
On 10/05/2012 01:59 PM, Alexander Graf wrote:
Do you mean that we add the "MemoryRegion bar0" in PCIDevice struct. Do the
>>> same thing that I was doing in e500_pcihost_initfn() in the k->init() (will
>>> add
>>> this) function of "e500-host-bridge"
>>>
>>> No, he means that you create a ne
mailto:a...@redhat.com]
>>>> Sent: Thursday, October 04, 2012 8:28 PM
>>>> To: Bhushan Bharat-R65777
>>>> Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org; ag...@suse.de
>>>> Subject: Re: [Qemu-devel] [PATCH 2/2] Adding BAR0 for e500 PCI
>>>> co
> -Original Message-
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Thursday, October 04, 2012 9:37 PM
> To: Bhushan Bharat-R65777
> Cc: Avi Kivity; qemu-devel@nongnu.org; qemu-...@nongnu.org
> Subject: Re: [Qemu-devel] [PATCH 2/2] Adding BAR0 for e500 PCI con
On 10/04/2012 06:50 PM, Alexander Graf wrote:
>>>
>>> No, it also meets (2). The PCI address space is identical to the CPU memory
>>> space in our mapping right now. So if the guest maps BAR0 somewhere, it
>>> automatically maps CCSR into CPU address space, which exposes it to PCI
>>> address
>>>
mailto:a...@redhat.com]
>>>> Sent: Thursday, October 04, 2012 8:28 PM
>>>> To: Bhushan Bharat-R65777
>>>> Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org; ag...@suse.de
>>>> Subject: Re: [Qemu-devel] [PATCH 2/2] Adding BAR0 for e500 PCI
>>>> co
> -Original Message-
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Thursday, October 04, 2012 9:37 PM
> To: Bhushan Bharat-R65777
> Cc: Avi Kivity; qemu-devel@nongnu.org; qemu-...@nongnu.org
> Subject: Re: [Qemu-devel] [PATCH 2/2] Adding BAR0 for e500 PCI con
>>>> Sent: Thursday, October 04, 2012 6:02 PM
>>>> To: Bhushan Bharat-R65777
>>>> Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org; ag...@suse.de;
>>>> Bhushan Bharat-
>>>> R65777
>>>> Subject: Re: [Qemu-devel] [PATCH 2/2] Adding
> -Original Message-
> From: Avi Kivity [mailto:a...@redhat.com]
> Sent: Thursday, October 04, 2012 8:28 PM
> To: Bhushan Bharat-R65777
> Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org; ag...@suse.de
> Subject: Re: [Qemu-devel] [PATCH 2/2] Adding BAR0 for e500 PCI con
On 04.10.2012, at 17:54, Andreas Färber wrote:
> Am 03.10.2012 13:50, schrieb Bharat Bhushan:
>> diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
>> index 197411d..c7ae2b6 100644
>> --- a/hw/ppc/e500.c
>> +++ b/hw/ppc/e500.c
>> @@ -518,6 +518,7 @@ void ppce500_init(PPCE500Params *params)
>>
>> /*
Am 03.10.2012 13:50, schrieb Bharat Bhushan:
> diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c
> index 197411d..c7ae2b6 100644
> --- a/hw/ppc/e500.c
> +++ b/hw/ppc/e500.c
> @@ -518,6 +518,7 @@ void ppce500_init(PPCE500Params *params)
>
> /* PCI */
> dev = qdev_create(NULL, "e500-pcihost");
>
g; ag...@suse.de; Bhushan
>> Bharat-
>> R65777
>> Subject: Re: [Qemu-devel] [PATCH 2/2] Adding BAR0 for e500 PCI controller
>>
>> On 10/03/2012 01:50 PM, Bharat Bhushan wrote:
>> > sysbus_connect_irq(s, 0, mpic[pci_irq_nrs[0]]); diff --git
>> &g
> -Original Message-
> From: Avi Kivity [mailto:a...@redhat.com]
> Sent: Thursday, October 04, 2012 6:02 PM
> To: Bhushan Bharat-R65777
> Cc: qemu-devel@nongnu.org; qemu-...@nongnu.org; ag...@suse.de; Bhushan Bharat-
> R65777
> Subject: Re: [Qemu-devel] [PATCH 2/2]
On 10/03/2012 01:50 PM, Bharat Bhushan wrote:
> sysbus_connect_irq(s, 0, mpic[pci_irq_nrs[0]]);
> diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c
> index 92b1dc0..16e4af2 100644
> --- a/hw/ppce500_pci.c
> +++ b/hw/ppce500_pci.c
> @@ -87,6 +87,7 @@ struct PPCE500PCIState {
> /* mmio maps
> -Original Message-
> From: Alexander Graf [mailto:ag...@suse.de]
> Sent: Wednesday, October 03, 2012 5:41 PM
> To: Bhushan Bharat-R65777
> Cc: qemu-devel qemu-devel; qemu-...@nongnu.org List; Bhushan Bharat-R65777;
> Avi
> Kivity
> Subject: Re: [PATCH 2/2] Adding BAR0 for e500 PCI cont
On 03.10.2012, at 13:50, Bharat Bhushan wrote:
> PCI Root complex have TYPE-1 configuration header while PCI endpoint
> have type-0 configuration header. The type-1 configuration header have
> a BAR (BAR0). In Freescale PCI controller BAR0 is used for mapping pci
> address space to CCSR address s
PCI Root complex have TYPE-1 configuration header while PCI endpoint
have type-0 configuration header. The type-1 configuration header have
a BAR (BAR0). In Freescale PCI controller BAR0 is used for mapping pci
address space to CCSR address space. This can used for 2 purposes: 1)
for MSI interrupt
21 matches
Mail list logo
