On 5/23/19 8:30 AM, Peter Maydell wrote:
> On Thu, 23 May 2019 at 14:16, Richard Henderson
> wrote:
>>
>> On 5/23/19 9:08 AM, Peter Maydell wrote:
Because the three different instructions perform the same operation with
reshuffled register arguments.
>>>
>>> Ah, so they do. Next question
On Thu, 23 May 2019 at 14:16, Richard Henderson
wrote:
>
> On 5/23/19 9:08 AM, Peter Maydell wrote:
> >> Because the three different instructions perform the same operation with
> >> reshuffled register arguments.
> >
> > Ah, so they do. Next question, how do I find out what the
> > order of argum
On 5/23/19 9:08 AM, Peter Maydell wrote:
>> Because the three different instructions perform the same operation with
>> reshuffled register arguments.
>
> Ah, so they do. Next question, how do I find out what the
> order of arguments in the above code means so I can compare
> it against the pseudo
On Thu, 23 May 2019 at 14:02, Richard Henderson
wrote:
>
> On 5/23/19 8:46 AM, Peter Maydell wrote:
> > On Sat, 18 May 2019 at 20:19, Richard Henderson
> > wrote:
> >>
> >> This replaces 3 target-specific implementations for BIT, BIF, and BSL.
> >>
> >> Signed-off-by: Richard Henderson
> >> @@ -
On 5/23/19 8:46 AM, Peter Maydell wrote:
> On Sat, 18 May 2019 at 20:19, Richard Henderson
> wrote:
>>
>> This replaces 3 target-specific implementations for BIT, BIF, and BSL.
>>
>> Signed-off-by: Richard Henderson
>> @@ -10916,13 +10925,13 @@ static void disas_simd_3same_logic(DisasContext
>>
On Sat, 18 May 2019 at 20:19, Richard Henderson
wrote:
>
> This replaces 3 target-specific implementations for BIT, BIF, and BSL.
>
> Signed-off-by: Richard Henderson
> @@ -10916,13 +10925,13 @@ static void disas_simd_3same_logic(DisasContext *s,
> uint32_t insn)
> return;
>
> case
This replaces 3 target-specific implementations for BIT, BIF, and BSL.
Signed-off-by: Richard Henderson
---
target/arm/translate-a64.h | 2 +
target/arm/translate.h | 3 --
target/arm/translate-a64.c | 15 ++--
target/arm/translate.c | 78 +++---
4 f
