From: James Hogan [ja...@albanarts.com] on behalf of James Hogan
Sent: Thursday, May 22, 2014 2:19 AM
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic; Petar Jovanovic; aurel...@aurel32.net
Subject: Re: [Qemu-devel] [PATCH 2/2] target-mips: implement
From: James Hogan [ja...@albanarts.com]
Sent: Thursday, May 22, 2014 2:03 AM
To: qemu-devel@nongnu.org
Cc: Petar Jovanovic; Petar Jovanovic; aurel...@aurel32.net
Subject: Re: [Qemu-devel] [PATCH 2/2] target-mips: implement UserLocal Register
> I think
] target-mips: implement UserLocal Register
> +target_ulong helper_rdhwr_ul(CPUMIPSState *env)
> +{
> +if ((env->hflags & MIPS_HFLAG_CP0) ||
> +(env->CP0_HWREna & (1 << 29))) {
> +return env->CP0_UserLocal;
> +} else {
>
On Friday 16 May 2014 20:13:34 Petar Jovanovic wrote:
> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> index 6c2014e..bb18fb8 100644
> --- a/target-mips/cpu.h
> +++ b/target-mips/cpu.h
> @@ -227,6 +227,7 @@ struct CPUMIPSState {
> target_ulong CP0_EntryLo0;
> target_ulong CP0_EntryL
Hi Petar,
On Friday 16 May 2014 20:13:34 Petar Jovanovic wrote:
> From: Petar Jovanovic
>
> From MIPS documentation (Volume III):
>
> UserLocal Register (CP0 Register 4, Select 2)
> Compliance Level: Recommended.
>
> The UserLocal register is a read-write register that is not interpreted by
>
On 05/16/2014 11:13 AM, Petar Jovanovic wrote:
> +target_ulong helper_rdhwr_ul(CPUMIPSState *env)
> +{
> +if ((env->hflags & MIPS_HFLAG_CP0) ||
> +(env->CP0_HWREna & (1 << 29))) {
> +return env->CP0_UserLocal;
> +} else {
> +helper_raise_exception(env, EXCP_RI);
> +
From: Petar Jovanovic
>From MIPS documentation (Volume III):
UserLocal Register (CP0 Register 4, Select 2)
Compliance Level: Recommended.
The UserLocal register is a read-write register that is not interpreted by
the hardware and conditionally readable via the RDHWR instruction.
This register
