Re: [Qemu-devel] [PATCH 2/6] e1000: Trivial implementation of various MAC registers

2015-10-25 Thread Leonid Bloch
Dear Jason, You were right both about the AIT and the FFMT! On a physical card, the reserved bits in both of them read as zeros, even if they were set to ones right before the reading. V2 of the patches, with all the remarks addressed, is on the way. Thanks again for your review. Leonid. ___ On

Re: [Qemu-devel] [PATCH 2/6] e1000: Trivial implementation of various MAC registers

2015-10-22 Thread Jason Wang
On 10/22/2015 10:05 PM, Leonid Bloch wrote: > On Thu, Oct 22, 2015 at 10:19 AM, Jason Wang wrote: >> >> >> On 10/21/2015 05:13 PM, Leonid Bloch wrote: >>> Hi Jason, thanks for the review! >>> >>> On Tue, Oct 20, 2015 at 8:40 AM, Jason Wang wrote: On 10/18/2015 03:53 PM, Leonid Bloch w

Re: [Qemu-devel] [PATCH 2/6] e1000: Trivial implementation of various MAC registers

2015-10-22 Thread Leonid Bloch
On Thu, Oct 22, 2015 at 10:19 AM, Jason Wang wrote: > > > > On 10/21/2015 05:13 PM, Leonid Bloch wrote: > > Hi Jason, thanks for the review! > > > > On Tue, Oct 20, 2015 at 8:40 AM, Jason Wang wrote: > >> > >> > >> On 10/18/2015 03:53 PM, Leonid Bloch wrote: > >>> These registers appear in Intel'

Re: [Qemu-devel] [PATCH 2/6] e1000: Trivial implementation of various MAC registers

2015-10-22 Thread Jason Wang
On 10/21/2015 05:13 PM, Leonid Bloch wrote: > Hi Jason, thanks for the review! > > On Tue, Oct 20, 2015 at 8:40 AM, Jason Wang wrote: >> >> >> On 10/18/2015 03:53 PM, Leonid Bloch wrote: >>> These registers appear in Intel's specs, but were not implemented. >>> These registers are now implemente

Re: [Qemu-devel] [PATCH 2/6] e1000: Trivial implementation of various MAC registers

2015-10-21 Thread Leonid Bloch
Hi Jason, thanks for the review! On Tue, Oct 20, 2015 at 8:40 AM, Jason Wang wrote: > > > > On 10/18/2015 03:53 PM, Leonid Bloch wrote: > > These registers appear in Intel's specs, but were not implemented. > > These registers are now implemented trivially, i.e. they are initiated > > with zero v

Re: [Qemu-devel] [PATCH 2/6] e1000: Trivial implementation of various MAC registers

2015-10-19 Thread Jason Wang
On 10/18/2015 03:53 PM, Leonid Bloch wrote: > These registers appear in Intel's specs, but were not implemented. > These registers are now implemented trivially, i.e. they are initiated > with zero values, and if they are RW, they can be written or read by the > driver, or read only if they are R

[Qemu-devel] [PATCH 2/6] e1000: Trivial implementation of various MAC registers

2015-10-18 Thread Leonid Bloch
These registers appear in Intel's specs, but were not implemented. These registers are now implemented trivially, i.e. they are initiated with zero values, and if they are RW, they can be written or read by the driver, or read only if they are R (essentially retaining their zero values). For these