Re: [Qemu-devel] [PATCH 2/8] target/ppc: Optimize emulation of vsl and vsr instructions

2019-06-26 Thread Richard Henderson
On 6/19/19 1:03 PM, Stefan Brankovic wrote: > Optimization of altivec instructions vsl and vsr(Vector Shift Left/Rigt). > Perform shift operation (left and right respectively) on 128 bit value of > register vA by value specified in bits 125-127 of register vB. Lowest 3 > bits in each byte element o

[Qemu-devel] [PATCH 2/8] target/ppc: Optimize emulation of vsl and vsr instructions

2019-06-19 Thread Stefan Brankovic
Optimization of altivec instructions vsl and vsr(Vector Shift Left/Rigt). Perform shift operation (left and right respectively) on 128 bit value of register vA by value specified in bits 125-127 of register vB. Lowest 3 bits in each byte element of register vB must be identical or result is undefin

Re: [Qemu-devel] [PATCH 2/8] target/ppc: Optimize emulation of vsl and vsr instructions

2019-06-17 Thread Stefan Brankovic
On 6.6.19. 19:03, Richard Henderson wrote: On 6/6/19 5:15 AM, Stefan Brankovic wrote: +tcg_gen_subi_i64(tmp, sh, 64); +tcg_gen_neg_i64(tmp, tmp); Better as tcg_gen_subfi_i64(tmp, 64, sh); I was aware there must be way of doing it in a single tcg invocation, but couldn't find r

Re: [Qemu-devel] [PATCH 2/8] target/ppc: Optimize emulation of vsl and vsr instructions

2019-06-06 Thread Richard Henderson
On 6/6/19 5:15 AM, Stefan Brankovic wrote: > +tcg_gen_subi_i64(tmp, sh, 64); > +tcg_gen_neg_i64(tmp, tmp); Better as tcg_gen_subfi_i64(tmp, 64, sh); r~

[Qemu-devel] [PATCH 2/8] target/ppc: Optimize emulation of vsl and vsr instructions

2019-06-06 Thread Stefan Brankovic
Optimization of altivec instructions vsl and vsr(Vector Shift Left/Rigt). Perform shift operation (left and right respectively) on 128 bit value of register vA by value specified in bits 125-127 of register vB. Lowest 3 bits in each byte element of register vB must be identical or result is undefin