Re: [Qemu-devel] [PATCH 21/28] target/riscv: Replace gen_store() with trans_store()

2018-10-13 Thread Richard Henderson
On 10/12/18 10:30 AM, Bastian Koppelmann wrote: > +static bool trans_store(DisasContext *ctx, arg_sb *a, int memop) gen_store. > { > -gen_store(ctx, OPC_RISC_SB, a->rs1, a->rs2, a->imm); > +TCGv t0 = tcg_temp_new(); > +TCGv dat = tcg_temp_new(); > +gen_get_gpr(t0, a->rs1); > +

[Qemu-devel] [PATCH 21/28] target/riscv: Replace gen_store() with trans_store()

2018-10-12 Thread Bastian Koppelmann
With decodetree we don't need to convert RISC-V opcodes into to MemOps as gen_store() did. Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn_trans/trans_rvi.inc.c | 31 -- target/riscv/translate.c| 34 -