- cycles fed into advance_ccount may (and on real hardware actually
do) depend on executed commands/pipeline/cache hits. Most of this
stuff may be counted at the translation time;
>>>
>>> Since CCOUNT, as seen by any one thread of execution, on real hw depends
>>> on cache hits, inte
On 05/24/2011 03:28 AM, Max Filippov wrote:
>>> - cycles fed into advance_ccount may (and on real hardware actually
>>> do) depend on executed commands/pipeline/cache hits. Most of this
>>> stuff may be counted at the translation time;
>>
>> Since CCOUNT, as seen by any one thread of execution, on
>> - cycles fed into advance_ccount may (and on real hardware actually
>> do) depend on executed commands/pipeline/cache hits. Most of this
>> stuff may be counted at the translation time;
>
> Since CCOUNT, as seen by any one thread of execution, on real hw depends
> on cache hits, interrupts, and
On 05/20/2011 02:30 PM, Max Filippov wrote:
> - cycles fed into advance_ccount may (and on real hardware actually
> do) depend on executed commands/pipeline/cache hits. Most of this
> stuff may be counted at the translation time;
Since CCOUNT, as seen by any one thread of execution, on real hw dep
> > By the way, do I understand it right that if I chain TBs than I need
> > to periodically check for pending interrupts myself, otherwise e.g.
> > "j $" will create uninterruptible infinite loop?
>
> No, it won't. It'll create a loop, but it'll be broken by the host
> signal handler. Notice no
On 05/20/2011 01:05 PM, Max Filippov wrote:
> By the way, do I understand it right that if I chain TBs than I need
> to periodically check for pending interrupts myself, otherwise e.g.
> "j $" will create uninterruptible infinite loop?
No, it won't. It'll create a loop, but it'll be broken by the
> > +if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT))
> > {
> > +int i;
> > +for (i = 0; i < env->config->nccompare; ++i) {
> > +if (env->sregs[CCOMPARE + i] - old_ccount <= d) {
> > +env->halted = 0;
> > +xtensa
On 05/17/2011 03:32 PM, Max Filippov wrote:
> +if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT)) {
> +int i;
> +for (i = 0; i < env->config->nccompare; ++i) {
> +if (env->sregs[CCOMPARE + i] - old_ccount <= d) {
> +env->halted = 0
See ISA, 4.4.6 (interrupt option), 4.4.7 (high priority interrupt
option) and 4.4.8 (timer interrupt option) for details.
Signed-off-by: Max Filippov
---
RFC -> PATCH changes:
- halt CPU on waiti, use qemu timer to wake up on CCOMPARE match;
- advance CCOUNT on TB exit, on exception and on RSR.CC
