Re: [Qemu-devel] [PATCH 23/28] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists

On 10/12/18 10:30 AM, Bastian Koppelmann wrote: > +static bool trans_arith(DisasContext *ctx, arg_arith *a, > +void(*func)(TCGv, TCGv, TCGv)) gen_arith. Otherwise, Reviewed-by: Richard Henderson r~

[Qemu-devel] [PATCH 23/28] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists

manual decoding in gen_arith() is not necessary with decodetree. Signed-off-by: Bastian Koppelmann Signed-off-by: Peer Adelt --- target/riscv/insn32.decode | 3 ++- target/riscv/insn_trans/trans_rvi.inc.c | 21 ++-- target/riscv/translate.c| 33