Signed-off-by: Hervé Poussineau <hpous...@reactos.org>
---
hw/timer/m48t59.c | 59 +++++++++++++++++++++++++++++++++++++++++++++
include/hw/timer/m48t59.h | 24 ++++++++++++++++++
2 files changed, 83 insertions(+)
diff --git a/hw/timer/m48t59.c b/hw/timer/m48t59.c
index c46b63c..c5e74ce 100644
--- a/hw/timer/m48t59.c
+++ b/hw/timer/m48t59.c
@@ -798,6 +798,24 @@ static int m48t59_init1(SysBusDevice *dev)
return 0;
}
+static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr)
+{
+ M48txxISAState *d = M48TXX_ISA(obj);
+ return m48t59_read(&d->state, addr);
+}
+
+static void m48txx_isa_write(Nvram *obj, uint32_t addr, uint32_t val)
+{
+ M48txxISAState *d = M48TXX_ISA(obj);
+ m48t59_write(&d->state, addr, val);
+}
+
+static void m48txx_isa_toggle_lock(Nvram *obj, int lock)
+{
+ M48txxISAState *d = M48TXX_ISA(obj);
+ m48t59_toggle_lock(&d->state, lock);
+}
+
static Property m48t59_isa_properties[] = {
DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74),
DEFINE_PROP_END_OF_LIST(),
@@ -806,10 +824,14 @@ static Property m48t59_isa_properties[] = {
static void m48txx_isa_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ NvramClass *nc = NVRAM_CLASS(klass);
dc->realize = m48t59_isa_realize;
dc->reset = m48t59_reset_isa;
dc->props = m48t59_isa_properties;
+ nc->read = m48txx_isa_read;
+ nc->write = m48txx_isa_write;
+ nc->toggle_lock = m48txx_isa_toggle_lock;
}
static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data)
@@ -820,13 +842,35 @@ static void m48txx_isa_concrete_class_init(ObjectClass
*klass, void *data)
u->info = *info;
}
+static uint32_t m48txx_sysbus_read(Nvram *obj, uint32_t addr)
+{
+ M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
+ return m48t59_read(&d->state, addr);
+}
+
+static void m48txx_sysbus_write(Nvram *obj, uint32_t addr, uint32_t val)
+{
+ M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
+ m48t59_write(&d->state, addr, val);
+}
+
+static void m48txx_sysbus_toggle_lock(Nvram *obj, int lock)
+{
+ M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
+ m48t59_toggle_lock(&d->state, lock);
+}
+
static void m48txx_sysbus_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+ NvramClass *nc = NVRAM_CLASS(klass);
k->init = m48t59_init1;
dc->reset = m48t59_reset_sysbus;
+ nc->read = m48txx_sysbus_read;
+ nc->write = m48txx_sysbus_write;
+ nc->toggle_lock = m48txx_sysbus_toggle_lock;
}
static void m48txx_sysbus_concrete_class_init(ObjectClass *klass, void *data)
@@ -837,12 +881,22 @@ static void m48txx_sysbus_concrete_class_init(ObjectClass
*klass, void *data)
u->info = *info;
}
+static const TypeInfo nvram_info = {
+ .name = TYPE_NVRAM,
+ .parent = TYPE_INTERFACE,
+ .class_size = sizeof(NvramClass),
+};
+
static const TypeInfo m48txx_sysbus_type_info = {
.name = TYPE_M48TXX_SYS_BUS,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(M48txxSysBusState),
.abstract = true,
.class_init = m48txx_sysbus_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_NVRAM },
+ { }
+ }
};
static const TypeInfo m48txx_isa_type_info = {
@@ -851,6 +905,10 @@ static const TypeInfo m48txx_isa_type_info = {
.instance_size = sizeof(M48txxISAState),
.abstract = true,
.class_init = m48txx_isa_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { TYPE_NVRAM },
+ { }
+ }
};
static void m48t59_register_types(void)
@@ -867,6 +925,7 @@ static void m48t59_register_types(void)
};
int i;
+ type_register_static(&nvram_info);
type_register_static(&m48txx_sysbus_type_info);
type_register_static(&m48txx_isa_type_info);
diff --git a/include/hw/timer/m48t59.h b/include/hw/timer/m48t59.h
index 8217522..ddbbda2 100644
--- a/include/hw/timer/m48t59.h
+++ b/include/hw/timer/m48t59.h
@@ -1,6 +1,9 @@
#ifndef NVRAM_H
#define NVRAM_H
+#include "qemu-common.h"
+#include "qom/object.h"
+
/* NVRAM helpers */
typedef uint32_t (*nvram_read_t)(void *private, uint32_t addr);
typedef void (*nvram_write_t)(void *private, uint32_t addr, uint32_t val);
@@ -34,4 +37,25 @@ M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base,
uint16_t size,
M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
uint32_t io_base, uint16_t size, int type);
+#define TYPE_NVRAM "nvram"
+
+#define NVRAM_CLASS(klass) \
+ OBJECT_CLASS_CHECK(NvramClass, (klass), TYPE_NVRAM)
+#define NVRAM_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(NvramClass, (obj), TYPE_NVRAM)
+#define NVRAM(obj) \
+ INTERFACE_CHECK(Nvram, (obj), TYPE_NVRAM)
+
+typedef struct Nvram {
+ Object parent;
+} Nvram;
+
+typedef struct NvramClass {
+ InterfaceClass parent;
+
+ uint32_t (*read)(Nvram *obj, uint32_t addr);
+ void (*write)(Nvram *obj, uint32_t addr, uint32_t val);
+ void (*toggle_lock)(Nvram *obj, int lock);
+} NvramClass;
+
#endif /* !NVRAM_H */
--
1.7.10.4
