Re: [Qemu-devel] [PATCH 3/4] target-ppc: ppc can be either endian

2014-04-29 Thread Greg Kurz
On Tue, 29 Apr 2014 11:14:12 +0200 Alexander Graf wrote: > > On 28.04.14 14:47, Andreas Färber wrote: > > [fixing Bharata's address] > > > > Am 28.04.2014 13:29, schrieb Greg Kurz: > >> POWER7, POWER7+ and POWER8 families use the ILE bit of the LPCR > >> special purpose register to decide the end

Re: [Qemu-devel] [PATCH 3/4] target-ppc: ppc can be either endian

2014-04-29 Thread Alexander Graf
On 28.04.14 14:47, Andreas Färber wrote: [fixing Bharata's address] Am 28.04.2014 13:29, schrieb Greg Kurz: POWER7, POWER7+ and POWER8 families use the ILE bit of the LPCR special purpose register to decide the endianness to use when entering interrupt handlers. When running a linux guest, thi

Re: [Qemu-devel] [PATCH 3/4] target-ppc: ppc can be either endian

2014-04-28 Thread Andreas Färber
[fixing Bharata's address] Am 28.04.2014 13:29, schrieb Greg Kurz: > POWER7, POWER7+ and POWER8 families use the ILE bit of the LPCR > special purpose register to decide the endianness to use when > entering interrupt handlers. When running a linux guest, this > provides a hint on the endianness u

[Qemu-devel] [PATCH 3/4] target-ppc: ppc can be either endian

2014-04-28 Thread Greg Kurz
POWER7, POWER7+ and POWER8 families use the ILE bit of the LPCR special purpose register to decide the endianness to use when entering interrupt handlers. When running a linux guest, this provides a hint on the endianness used by the kernel. From a qemu point of view, the information is needed for