Re: [Qemu-devel] [PATCH 3/5 v3] RISC-V: Fixes to CSR_* register macros.

2019-02-06 Thread Alistair Francis
On Tue, Jan 29, 2019 at 6:56 PM Jim Wilson wrote: > > This adds some missing CSR_* register macros, and documents some as being > priv v1.9.1 specific. > > Signed-off-by: Jim Wilson Reviewed-by: Alistair Francis Alistair > --- > target/riscv/cpu_bits.h | 35 +-

[Qemu-devel] [PATCH 3/5 v3] RISC-V: Fixes to CSR_* register macros.

2019-01-29 Thread Jim Wilson
This adds some missing CSR_* register macros, and documents some as being priv v1.9.1 specific. Signed-off-by: Jim Wilson --- target/riscv/cpu_bits.h | 35 +-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cp