stfa/stdfa/stqfa instructions should raise fp_disabled exceptions
if %pstate.PEF==0 or %fprs.FEF==0.
Signed-off-by: Tsuneo Saito <tsnsa...@gmail.com>
---
target-sparc/translate.c | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 95e78a3..94c1000 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -4729,6 +4729,8 @@ static void disas_sparc_insn(DisasContext * dc)
switch (xop) {
#ifdef TARGET_SPARC64
case 0x34: /* V9 stfa */
+ if (gen_trap_ifnofpu(dc, cpu_cond))
+ goto jmp_insn;
gen_stf_asi(cpu_addr, insn, 4, rd);
break;
case 0x36: /* V9 stqfa */
@@ -4736,6 +4738,8 @@ static void disas_sparc_insn(DisasContext * dc)
TCGv_i32 r_const;
CHECK_FPU_FEATURE(dc, FLOAT128);
+ if (gen_trap_ifnofpu(dc, cpu_cond))
+ goto jmp_insn;
r_const = tcg_const_i32(7);
gen_helper_check_align(cpu_addr, r_const);
tcg_temp_free_i32(r_const);
@@ -4743,6 +4747,8 @@ static void disas_sparc_insn(DisasContext * dc)
}
break;
case 0x37: /* V9 stdfa */
+ if (gen_trap_ifnofpu(dc, cpu_cond))
+ goto jmp_insn;
gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd));
break;
case 0x3c: /* V9 casa */
--
1.7.5.4
