From: Rob Herring
Adds support for Calxeda's Highbank SoC.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
Signed-off-by: Peter Maydell
---
Makefile.target |1 +
hw/highbank.c | 330 +++
2 files changed, 331 insertions(+), 0
Am 07.01.2012 10:55, schrieb Igor Mitsyanko:
> On 06.01.2012 11:11 PM, Andreas Färber wrote:
>> Am 06.01.2012 20:10, schrieb Igor Mitsyanko:
>>> On 01/06/2012 10:45 PM, Peter Maydell wrote:
On 6 January 2012 18:37, Igor Mitsyanko wrote:
> On 01/06/2012 12:02 AM, Mark Langsdorf wrote:
>>>
On 06.01.2012 11:11 PM, Andreas Färber wrote:
Am 06.01.2012 20:10, schrieb Igor Mitsyanko:
On 01/06/2012 10:45 PM, Peter Maydell wrote:
On 6 January 2012 18:37, Igor Mitsyanko wrote:
On 01/06/2012 12:02 AM, Mark Langsdorf wrote:
+if (!cpu_model) {
+cpu_model = "cortex-a9";
+
Am 07.01.2012 04:14, schrieb Peter Maydell:
> On 6 January 2012 20:11, Andreas Färber wrote:
>> Not sure how hardcoding the cpu_model would work with CPU features,
>> would they be still included or stripped out before. Peter?
>
> Interesting question. It's certainly more likely to work to have
>
On 6 January 2012 21:16, Mark Langsdorf wrote:
> Assuming that I'm going to need save/restore support, what's
> the proper syntax for saving uint32_t *regs? All the uses I
> can find seem to be for an array of structs, not an array
> of ints, and I keep hoping there's a simpler way.
VMSTATE_UINT3
On 6 January 2012 20:11, Andreas Färber wrote:
> Not sure how hardcoding the cpu_model would work with CPU features,
> would they be still included or stripped out before. Peter?
Interesting question. It's certainly more likely to work to have
a board where the only tweak you made to the CPU was
On 01/06/2012 10:29 AM, Peter Maydell wrote:
> On 5 January 2012 20:02, Mark Langsdorf wrote:
>> +static void hb_regs_write(void *opaque, target_phys_addr_t offset,
>> + uint64_t value, unsigned size)
>> +{
>> +uint32_t *regs = opaque;
>> +
>> +if (offset == 0xf00)
Am 06.01.2012 20:10, schrieb Igor Mitsyanko:
> On 01/06/2012 10:45 PM, Peter Maydell wrote:
>> On 6 January 2012 18:37, Igor Mitsyanko wrote:
>>> On 01/06/2012 12:02 AM, Mark Langsdorf wrote:
+if (!cpu_model) {
+cpu_model = "cortex-a9";
+}
>>>
>>>
>>> Google said the
On 01/06/2012 10:45 PM, Peter Maydell wrote:
On 6 January 2012 18:37, Igor Mitsyanko wrote:
On 01/06/2012 12:02 AM, Mark Langsdorf wrote:
+if (!cpu_model) {
+cpu_model = "cortex-a9";
+}
Google said there is only cortexA9-based Highbank SoC version, maybe you
should just hard
On 01/06/2012 12:37 PM, Igor Mitsyanko wrote:
> On 01/06/2012 12:02 AM, Mark Langsdorf wrote:
>
> Hello, Mark. According to technical specification on Calxeda website,
> highbank SoC has SD 3.0 host controller, are you planning to implement
> it in qemu? I'm asking because I recently have submitte
On 6 January 2012 18:37, Igor Mitsyanko wrote:
> On 01/06/2012 12:02 AM, Mark Langsdorf wrote:
>> + if (!cpu_model) {
>> + cpu_model = "cortex-a9";
>> + }
>
>
> Google said there is only cortexA9-based Highbank SoC version, maybe you
> should just hardcode cpu model?
This is just boi
On 01/06/2012 12:02 AM, Mark Langsdorf wrote:
Hello, Mark. According to technical specification on Calxeda website,
highbank SoC has SD 3.0 host controller, are you planning to implement
it in qemu? I'm asking because I recently have submitted a patch
implementing SD 2.0 host controller, and i
Am 05.01.2012 21:02, schrieb Mark Langsdorf:
> From: Rob Herring
>
> Adds support for Calxeda's Highbank SoC.
>
> Signed-off-by: Rob Herring
> Signed-off-by: Mark Langsdorf
> ---
> diff --git a/hw/highbank.c b/hw/highbank.c
> new file mode 100644
> index 000..73b6564
> --- /dev/null
> +++
On 6 January 2012 17:34, Mark Langsdorf wrote:
> On 01/06/2012 11:04 AM, Peter Maydell wrote:
>> On 6 January 2012 16:58, Mark Langsdorf wrote:
> + if (load_image_targphys("sysram.bin", 0xfff88000, 0x8000) < 0) {
> + fprintf(stderr, "Unable to load sysram.bin\n");
> +
On 01/06/2012 11:04 AM, Peter Maydell wrote:
> On 6 January 2012 16:58, Mark Langsdorf wrote:
>> On 01/06/2012 10:29 AM, Peter Maydell wrote:
+sysram = g_new(MemoryRegion, 1);
+memory_region_init_ram(sysram, "highbank.sysram", 0x8000);
+memory_region_add_subregion(sysme
On 6 January 2012 16:58, Mark Langsdorf wrote:
> On 01/06/2012 10:29 AM, Peter Maydell wrote:
>>> + /* Override default RAM size */
>>> + if (ram_size == 0x800) {
>>> + if (sizeof(long) == 8) {
>>> + ram_size = 0xff90;
>>> + } else {
>>> + ram_size
On 01/06/2012 10:29 AM, Peter Maydell wrote:
> On 5 January 2012 20:02, Mark Langsdorf wrote:
>> From: Rob Herring
>>
>> Adds support for Calxeda's Highbank SoC.
>
> Is there a test kernel image/etc we can use to confirm that this all works?
The 3.2 kernel should have all the necessary support
On 5 January 2012 20:02, Mark Langsdorf wrote:
> From: Rob Herring
>
> Adds support for Calxeda's Highbank SoC.
Is there a test kernel image/etc we can use to confirm that this all works?
> --- /dev/null
> +++ b/hw/highbank.c
> @@ -0,0 +1,227 @@
> +/*
> + * Calxeda Highbank SoC emulation
Is it
From: Rob Herring
Adds support for Calxeda's Highbank SoC.
Signed-off-by: Rob Herring
Signed-off-by: Mark Langsdorf
---
Makefile.target |1 +
hw/highbank.c | 227 +++
2 files changed, 228 insertions(+), 0 deletions(-)
create mode 100
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