On 03/03/2019 23:35, Richard Henderson wrote:
> On 3/3/19 9:23 AM, Mark Cave-Ayland wrote:
>> static inline void get_cpu_vsrh(TCGv_i64 dst, int n)
>> {
>> -if (n < 32) {
>> -get_fpr(dst, n);
>> -} else {
>> -get_avr64(dst, n - 32, true);
>> -}
>> +tcg_gen_ld_i64(d
On 3/3/19 9:23 AM, Mark Cave-Ayland wrote:
> static inline void get_cpu_vsrh(TCGv_i64 dst, int n)
> {
> -if (n < 32) {
> -get_fpr(dst, n);
> -} else {
> -get_avr64(dst, n - 32, true);
> -}
> +tcg_gen_ld_i64(dst, cpu_env, vsrh_offset(n));
> }
>
> static inline v
Now that the VSX registers are all in host endian order, there is no need to
go via different accessors depending upon the register number. Instead the
high and low parts can be accessed directly via vsrh_offset() and vsrl_offset()
accordingly.
Signed-off-by: Mark Cave-Ayland
---
target/ppc/tran
