Re: [Qemu-devel] [PATCH RFC] target/openrisc: Support non-busy idle state using PMR SPR

2017-04-25 Thread Richard Henderson
On 04/25/2017 04:18 PM, Stafford Horne wrote: On Tue, Apr 25, 2017 at 12:11:00PM +0200, Richard Henderson wrote: On 04/23/2017 11:54 PM, Stafford Horne wrote: The OpenRISC architecture has the Power Management Register (PMR) special purpose register to manage cpu power states. The interesting

Re: [Qemu-devel] [PATCH RFC] target/openrisc: Support non-busy idle state using PMR SPR

2017-04-25 Thread Stafford Horne
On Tue, Apr 25, 2017 at 12:11:00PM +0200, Richard Henderson wrote: > On 04/23/2017 11:54 PM, Stafford Horne wrote: > > The OpenRISC architecture has the Power Management Register (PMR) > > special purpose register to manage cpu power states. The interesting > > modes are: > > > > * Doze Mode (D

Re: [Qemu-devel] [PATCH RFC] target/openrisc: Support non-busy idle state using PMR SPR

2017-04-25 Thread Richard Henderson
On 04/23/2017 11:54 PM, Stafford Horne wrote: The OpenRISC architecture has the Power Management Register (PMR) special purpose register to manage cpu power states. The interesting modes are: * Doze Mode (DME) - Stop cpu except timer & pic - wake on interrupt * Sleep Mode (SME) - Stop cpu a

[Qemu-devel] [PATCH RFC] target/openrisc: Support non-busy idle state using PMR SPR

2017-04-23 Thread Stafford Horne
The OpenRISC architecture has the Power Management Register (PMR) special purpose register to manage cpu power states. The interesting modes are: * Doze Mode (DME) - Stop cpu except timer & pic - wake on interrupt * Sleep Mode (SME) - Stop cpu and all units - wake on interrupt * Suspend Model