[Qemu-devel] [PATCH RFC 0/7] Translate guest vector operations to host vector operations

2014-10-16 Thread Kirill Batuzov
> (4) Consider supporting generic vector operations in the TCG? I gave it a go and was quite happy with the result. I have implemented the add_i32x4 opcode which is addition of 128-bit vectors composed of four 32-bit integers and used it to translate NEON vadd.i32 to SSE paddd instruction. I used

Re: [Qemu-devel] [PATCH RFC 0/7] Translate guest vector operations to host vector operations

2014-10-16 Thread Alex Bennée
Kirill Batuzov writes: >> (4) Consider supporting generic vector operations in the TCG? > > I gave it a go and was quite happy with the result. I have implemented the > add_i32x4 > opcode which is addition of 128-bit vectors composed of four 32-bit integers > and used it to translate NEON vadd.

Re: [Qemu-devel] [PATCH RFC 0/7] Translate guest vector operations to host vector operations

2014-10-16 Thread Kirill Batuzov
On Thu, 16 Oct 2014, Alex Bennée wrote: > > > > From Valgrind experience there are enough genericism. Valgrind can translate > > SSE, AltiVec and NEON instructions to vector opcodes. Most of the opcodes > > are > > reused between instruction sets. > > Doesn't Valgrind have the advantage of same-

Re: [Qemu-devel] [PATCH RFC 0/7] Translate guest vector operations to host vector operations

2014-11-11 Thread Kirill Batuzov
On Thu, 16 Oct 2014, Kirill Batuzov wrote: > > (4) Consider supporting generic vector operations in the TCG? > > I gave it a go and was quite happy with the result. I have implemented the > add_i32x4 > opcode which is addition of 128-bit vectors composed of four 32-bit integers > and used it to