Am 05.08.2013 00:04, schrieb Aurélien Jarno:
On Mon, Jul 29, 2013 at 10:35:31PM +0200, Stefan Weil wrote:
Am 27.07.2013 22:58, schrieb Stefan Weil:
Am 27.07.2013 22:43, schrieb Andreas Färber:
Am 27.07.2013 21:37, schrieb Stefan Weil:
Am 27.07.2013 19:43, schrieb Peter Maydell:
On 27 July
On 2013-08-05 10:45, Andreas Färber wrote:
Am 05.08.2013 00:04, schrieb Aurélien Jarno:
On Mon, Jul 29, 2013 at 10:35:31PM +0200, Stefan Weil wrote:
Am 27.07.2013 22:58, schrieb Stefan Weil:
Am 27.07.2013 22:43, schrieb Andreas Färber:
Am 27.07.2013 21:37, schrieb Stefan Weil:
Am 27.07.2013
On Mon, Aug 05, 2013 at 07:19:08AM +0200, Stefan Weil wrote:
Am 05.08.2013 00:37, schrieb Peter Maydell:
On 4 August 2013 23:04, Aurélien Jarno aurel...@aurel32.net wrote:
The real hardware probably returns all 1 or all 0 for addresses not
decoded to a device. This is what QEMU should
On Mon, Aug 05, 2013 at 10:45:31AM +0200, Andreas Färber wrote:
Am 05.08.2013 00:04, schrieb Aurélien Jarno:
On Mon, Jul 29, 2013 at 10:35:31PM +0200, Stefan Weil wrote:
Am 27.07.2013 22:58, schrieb Stefan Weil:
Am 27.07.2013 22:43, schrieb Andreas Färber:
Am 27.07.2013 21:37, schrieb
Am 05.08.2013 15:31, schrieb Aurélien Jarno:
On Mon, Aug 05, 2013 at 10:45:31AM +0200, Andreas Färber wrote:
Am 05.08.2013 00:04, schrieb Aurélien Jarno:
On Mon, Jul 29, 2013 at 10:35:31PM +0200, Stefan Weil wrote:
Am 27.07.2013 22:58, schrieb Stefan Weil:
Am 27.07.2013 22:43, schrieb Andreas
Andreas Färber a écrit :
[snip]
Have you tested Jan's patches limiting the new unassigned read value -1
to PIO?
I have tried this patches, and they don't fix the problem.
Too bad. So what do you propose? Restoring #ifdef and using
empty_slot_init() have been suggested so far, any other
On Mon, Aug 05, 2013 at 03:53:08PM +0200, Hervé Poussineau wrote:
Andreas Färber a écrit :
[snip]
Have you tested Jan's patches limiting the new unassigned read value -1
to PIO?
I have tried this patches, and they don't fix the problem.
Too bad. So what do you propose? Restoring #ifdef
On 5 August 2013 15:07, Aurélien Jarno aurel...@aurel32.net wrote:
On Mon, Aug 05, 2013 at 03:53:08PM +0200, Hervé Poussineau wrote:
Another idea (not tested): override the
CPUClass-do_unassigned_level on board level, to only raise IBE and
no DBE.
This sounds like a bit of a layering
On Mon, Jul 29, 2013 at 10:35:31PM +0200, Stefan Weil wrote:
Am 27.07.2013 22:58, schrieb Stefan Weil:
Am 27.07.2013 22:43, schrieb Andreas Färber:
Am 27.07.2013 21:37, schrieb Stefan Weil:
Am 27.07.2013 19:43, schrieb Peter Maydell:
On 27 July 2013 17:18, Hervé Poussineau
On 4 August 2013 23:04, Aurélien Jarno aurel...@aurel32.net wrote:
The real hardware probably returns all 1 or all 0 for addresses not
decoded to a device. This is what QEMU should model, and it should
not trigger a DBE or IBE exception. Looking at the current MIPS
documentation, Bus Error is
Am 05.08.2013 00:37, schrieb Peter Maydell:
On 4 August 2013 23:04, Aurélien Jarno aurel...@aurel32.net wrote:
The real hardware probably returns all 1 or all 0 for addresses not
decoded to a device. This is what QEMU should model, and it should
not trigger a DBE or IBE exception. Looking at
Am 27.07.2013 22:58, schrieb Stefan Weil:
Am 27.07.2013 22:43, schrieb Andreas Färber:
Am 27.07.2013 21:37, schrieb Stefan Weil:
Am 27.07.2013 19:43, schrieb Peter Maydell:
On 27 July 2013 17:18, Hervé Poussineau hpous...@reactos.org wrote:
Another solution would be to add a big dummy memory
c658b94f6e8c206c59d02aa6fbac285b86b53d2c (cpu: Turn cpu_unassigned_access()
into a CPUState hook) made MIPS raise exceptions when accessing
invalid memory for data, by unconditionally calling CPUState unassigned hook.
While this seems to be the right behaviour, this breaks a lot of guests
(Linux
Am 27.07.2013 18:18, schrieb Hervé Poussineau:
c658b94f6e8c206c59d02aa6fbac285b86b53d2c (cpu: Turn cpu_unassigned_access()
into a CPUState hook) made MIPS raise exceptions when accessing
invalid memory for data, by unconditionally calling CPUState unassigned hook.
While this seems to be the
On 27 July 2013 17:18, Hervé Poussineau hpous...@reactos.org wrote:
Another solution would be to add a big dummy memory regions on all MIPS boards
to catch memory accesses and not raise an exception. However, this means that
each MIPS board will have its own unassigned memory handler, different
Am 27.07.2013 21:37, schrieb Stefan Weil:
Am 27.07.2013 19:43, schrieb Peter Maydell:
On 27 July 2013 17:18, Hervé Poussineau hpous...@reactos.org wrote:
Another solution would be to add a big dummy memory regions on all MIPS
boards
to catch memory accesses and not raise an exception.
Am 27.07.2013 19:43, schrieb Peter Maydell:
On 27 July 2013 17:18, Hervé Poussineau hpous...@reactos.org wrote:
Another solution would be to add a big dummy memory regions on all MIPS
boards
to catch memory accesses and not raise an exception. However, this means that
each MIPS board will
On 27 July 2013 21:43, Andreas Färber afaer...@suse.de wrote:
Am 27.07.2013 21:37, schrieb Stefan Weil:
Am 27.07.2013 19:43, schrieb Peter Maydell:
On 27 July 2013 17:18, Hervé Poussineau hpous...@reactos.org wrote:
Another solution would be to add a big dummy memory regions on all MIPS
Am 27.07.2013 22:43, schrieb Andreas Färber:
Am 27.07.2013 21:37, schrieb Stefan Weil:
Am 27.07.2013 19:43, schrieb Peter Maydell:
On 27 July 2013 17:18, Hervé Poussineau hpous...@reactos.org wrote:
Another solution would be to add a big dummy memory regions on all MIPS
boards
to catch
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