Re: [Qemu-devel] [PATCH for-2.4 1/2] target-mips: fix page fault address for LWL/LWR/LDL/LDR

2015-07-15 Thread Leon Alrae
On 14/07/2015 16:45, Aurelien Jarno wrote: > When a LWL, LWR, LDL or LDR instruction triggers a page fault, QEMU > currently reports the aligned address in CP0 BadVAddr, while the Windows > NT kernel expects the unaligned address. > > This patch adds a byte access with the unaligned address at the

[Qemu-devel] [PATCH for-2.4 1/2] target-mips: fix page fault address for LWL/LWR/LDL/LDR

2015-07-14 Thread Aurelien Jarno
When a LWL, LWR, LDL or LDR instruction triggers a page fault, QEMU currently reports the aligned address in CP0 BadVAddr, while the Windows NT kernel expects the unaligned address. This patch adds a byte access with the unaligned address at the beginning of the LWL/LWR/LDL/LDR instructions to pos