On 08/07/2015 10:15 PM, Eduardo Habkost wrote:
The existing i440fx initialization code sets a PCI config register that
isn't documented anywhere in the Intel 440FX datasheet. Register 0x57 is
DRAMC (DRAM Control) and has nothing to do with the RAM size.
This was implemented in commit
On 08/17/2015 08:58 PM, Eduardo Habkost wrote:
On Thu, Aug 13, 2015 at 11:30:57AM -0400, Richard Smith wrote:
On 08/09/2015 09:48 PM, Ed Swierk wrote:
References to coreboot commits: * Original commit adding code reading
register offsets 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57 to
On Thu, Aug 13, 2015 at 11:30:57AM -0400, Richard Smith wrote:
On 08/09/2015 09:48 PM, Ed Swierk wrote:
References to coreboot commits: * Original commit adding code reading
register offsets 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57 to
Intel 440bx code in coreboot:
On 08/09/2015 09:48 PM, Ed Swierk wrote:
References to coreboot commits: * Original commit adding code reading
register offsets 0x5a, 0x5b, 0x5c, 0x5d, 0x5e, 0x5f, 0x56, 0x57 to
Intel 440bx code in coreboot:
cb8eab482ff09ec256456312ef2d6e7710123551
I have vague recollection I may have been
That original coreboot code certainly looks like a mistake. Thanks for
helping close the decade-long loop.
On Fri, Aug 7, 2015 at 12:15 PM, Eduardo Habkost ehabk...@redhat.com
wrote:
The existing i440fx initialization code sets a PCI config register that
isn't documented anywhere in the
The existing i440fx initialization code sets a PCI config register that
isn't documented anywhere in the Intel 440FX datasheet. Register 0x57 is
DRAMC (DRAM Control) and has nothing to do with the RAM size.
This was implemented in commit ec5f92ce6ac8ec09056be77e03c941be188648fa
because old
