Re: [Qemu-devel] [PATCH for-2.9 1/2] intel_iommu: check validity for GAW bits in CE

2016-12-11 Thread Peter Xu
On Thu, Dec 08, 2016 at 10:21:35AM +0800, Jason Wang wrote: > > > On 2016年12月08日 10:16, Peter Xu wrote: > >On Thu, Dec 08, 2016 at 10:02:15AM +0800, Jason Wang wrote: > >> > >>On 2016年12月07日 13:52, Peter Xu wrote: > >>>Currently vt-d Context Entry (CE) only allows 39/48 bits address width. >

Re: [Qemu-devel] [PATCH for-2.9 1/2] intel_iommu: check validity for GAW bits in CE

2016-12-07 Thread Jason Wang
On 2016年12月08日 10:16, Peter Xu wrote: On Thu, Dec 08, 2016 at 10:02:15AM +0800, Jason Wang wrote: On 2016年12月07日 13:52, Peter Xu wrote: Currently vt-d Context Entry (CE) only allows 39/48 bits address width. If guest software configured more than that, we complain and force shrink to the

Re: [Qemu-devel] [PATCH for-2.9 1/2] intel_iommu: check validity for GAW bits in CE

2016-12-07 Thread Peter Xu
On Thu, Dec 08, 2016 at 10:02:15AM +0800, Jason Wang wrote: > > > On 2016年12月07日 13:52, Peter Xu wrote: > >Currently vt-d Context Entry (CE) only allows 39/48 bits address width. > >If guest software configured more than that, we complain and force > >shrink to the maximum supported, which is

Re: [Qemu-devel] [PATCH for-2.9 1/2] intel_iommu: check validity for GAW bits in CE

2016-12-07 Thread Jason Wang
On 2016年12月07日 13:52, Peter Xu wrote: Currently vt-d Context Entry (CE) only allows 39/48 bits address width. If guest software configured more than that, we complain and force shrink to the maximum supported, which is 48bits. Signed-off-by: Peter Xu ---

[Qemu-devel] [PATCH for-2.9 1/2] intel_iommu: check validity for GAW bits in CE

2016-12-06 Thread Peter Xu
Currently vt-d Context Entry (CE) only allows 39/48 bits address width. If guest software configured more than that, we complain and force shrink to the maximum supported, which is 48bits. Signed-off-by: Peter Xu --- hw/i386/intel_iommu.c | 12 +++-