On Fri, 26 Jul 2019 at 08:37, Laurent Desnogues
wrote:
> On Fri, Jul 26, 2019 at 9:24 AM Alex Bennée wrote:
> > Peter Maydell writes:
> > > I wonder if we should put 0x51 (ascii 'Q') in the PARTNUM field;
> > > then if somebody really needs to distinguish QEMU from random
> > > other software-mo
On Fri, Jul 26, 2019 at 9:24 AM Alex Bennée wrote:
>
>
> Peter Maydell writes:
>
> > On Tue, 23 Jul 2019 at 12:33, Alex Bennée wrote:
[...]
> > /*
> > * Reset MIDR so the guest doesn't mistake our 'max' CPU type for a real
> > * one and try to apply errata workarounds or use impdef features
Peter Maydell writes:
> On Tue, 23 Jul 2019 at 12:33, Alex Bennée wrote:
>>
>> While most features are now detected by probing the ID_* registers
>> kernels can (and do) use MIDR_EL1 for working out of they have to
>> apply errata. This can trip up warnings in the kernel as it tries to
>> work
On Tue, 23 Jul 2019 at 12:33, Alex Bennée wrote:
>
> While most features are now detected by probing the ID_* registers
> kernels can (and do) use MIDR_EL1 for working out of they have to
> apply errata. This can trip up warnings in the kernel as it tries to
> work out if it should apply workaroun
While most features are now detected by probing the ID_* registers
kernels can (and do) use MIDR_EL1 for working out of they have to
apply errata. This can trip up warnings in the kernel as it tries to
work out if it should apply workarounds to features that don't
actually exist in the reported CPU
