On Thu, Jun 25, 2015 at 01:59:38PM -0600, Alex Williamson wrote:
> On Wed, 2015-06-24 at 20:52 +1000, Alexey Kardashevskiy wrote:
> > On 06/23/2015 04:44 PM, David Gibson wrote:
> > > On Thu, Jun 18, 2015 at 09:37:22PM +1000, Alexey Kardashevskiy wrote:
> > >>
> > >> (cut-n-paste from kernel patchs
On Wed, 2015-06-24 at 20:52 +1000, Alexey Kardashevskiy wrote:
> On 06/23/2015 04:44 PM, David Gibson wrote:
> > On Thu, Jun 18, 2015 at 09:37:22PM +1000, Alexey Kardashevskiy wrote:
> >>
> >> (cut-n-paste from kernel patchset)
> >>
> >> Each Partitionable Endpoint (IOMMU group) has an address rang
On 06/23/2015 04:44 PM, David Gibson wrote:
On Thu, Jun 18, 2015 at 09:37:22PM +1000, Alexey Kardashevskiy wrote:
(cut-n-paste from kernel patchset)
Each Partitionable Endpoint (IOMMU group) has an address range on a PCI bus
where devices are allowed to do DMA. These ranges are called DMA wind
On Thu, Jun 18, 2015 at 09:37:22PM +1000, Alexey Kardashevskiy wrote:
>
> (cut-n-paste from kernel patchset)
>
> Each Partitionable Endpoint (IOMMU group) has an address range on a PCI bus
> where devices are allowed to do DMA. These ranges are called DMA windows.
> By default, there is a single
(cut-n-paste from kernel patchset)
Each Partitionable Endpoint (IOMMU group) has an address range on a PCI bus
where devices are allowed to do DMA. These ranges are called DMA windows.
By default, there is a single DMA window, 1 or 2GB big, mapped at zero
on a PCI bus.
PAPR defines a DDW RTAS AP
