On Fri, Apr 24, 2015 at 01:28:41PM -0700, Peter Crosthwaite wrote:
> Add the ARM cortex A53 processor definition. Similar to A57, but with
> different L1 I cache policy, phys addr size and different cache
> geometries. The cache sizes is implementation configurable, but use
> these values (from Xil
Add the ARM cortex A53 processor definition. Similar to A57, but with
different L1 I cache policy, phys addr size and different cache
geometries. The cache sizes is implementation configurable, but use
these values (from Xilinx Zynq MPSoC) as a default until cache size
configurability is added.
Si
