Re: [Qemu-devel] [PATCH v1] target-s390x: fix risbg handling

2017-07-03 Thread David Hildenbrand
On 01.07.2017 22:27, Richard Henderson wrote: > On 06/25/2017 03:19 PM, Aurelien Jarno wrote: >> On 2017-06-23 01:12, David Hildenbrand wrote: >>> If we have for example: r3 contains 0x >>> ec 33 3f bf 61 55 risbg %r3,%r3,63,191,97 >>> >>> We want to rotate 33 to the le

Re: [Qemu-devel] [PATCH v1] target-s390x: fix risbg handling

2017-07-01 Thread Richard Henderson
On 06/25/2017 03:19 PM, Aurelien Jarno wrote: On 2017-06-23 01:12, David Hildenbrand wrote: If we have for example: r3 contains 0x ec 33 3f bf 61 55 risbg %r3,%r3,63,191,97 We want to rotate 33 to the left and only keep MSB bit 63 of that. So the result is then exac

Re: [Qemu-devel] [PATCH v1] target-s390x: fix risbg handling

2017-06-25 Thread Aurelien Jarno
On 2017-06-23 01:12, David Hildenbrand wrote: > If we have for example: r3 contains 0x > ec 33 3f bf 61 55 risbg %r3,%r3,63,191,97 > > We want to rotate 33 to the left and only keep MSB bit 63 of that. So the > result is then exactly 1 (we're reading the sign of the 32

[Qemu-devel] [PATCH v1] target-s390x: fix risbg handling

2017-06-22 Thread David Hildenbrand
If we have for example: r3 contains 0x ec 33 3f bf 61 55 risbg %r3,%r3,63,191,97 We want to rotate 33 to the left and only keep MSB bit 63 of that. So the result is then exactly 1 (we're reading the sign of the 32 bit value). Current code assumes that we can do that vi