Privileged control and status register helpers and page fault handling.
Signed-off-by: Michael Clark
---
target/riscv/helper.c| 494 +
target/riscv/helper.h| 78 ++
target/riscv/op_helper.c | 707 +++
3 file
> +if (env->priv_ver >= PRIV_VERSION_1_10_0) {
> +if (get_field(env->satp, SATP_MODE) == VM_1_09_MBARE) {
> +mode = PRV_M;
> +}
> +} else {
> +if (get_field(env->mstatus, MSTATUS_VM) == VM_1_10_MBARE) {
> +mode = PRV_M;
> +}
> +}
On Tue, Jan 2, 2018 at 11:12 PM, Richard Henderson
wrote:
>> +case CSR_MISA: {
>> +if (!(val_to_write & (1L << ('F' - 'A' {
>> +val_to_write &= ~(1L << ('D' - 'A'));
>> +}
>> +
>> +/* allow MAFDC bits in MISA to be modified */
>> +target_ulong ma
On 01/10/2018 02:35 AM, Stefan O'Rear wrote:
> On Tue, Jan 2, 2018 at 11:12 PM, Richard Henderson
> wrote:
>>> +case CSR_MISA: {
>>> +if (!(val_to_write & (1L << ('F' - 'A' {
>>> +val_to_write &= ~(1L << ('D' - 'A'));
>>> +}
>>> +
>>> +/* allow MAFDC bit
On 01/02/2018 04:44 PM, Michael Clark wrote:
> +target_ulong mode = env->priv;
> +if (access_type != MMU_INST_FETCH) {
> +if (get_field(env->mstatus, MSTATUS_MPRV)) {
> +mode = get_field(env->mstatus, MSTATUS_MPP);
> +}
> +}
> +if (env->priv_ver >= PRIV_V
On Wed, Jan 3, 2018 at 8:12 PM, Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 01/02/2018 04:44 PM, Michael Clark wrote:
> > +target_ulong mode = env->priv;
> > +if (access_type != MMU_INST_FETCH) {
> > +if (get_field(env->mstatus, MSTATUS_MPRV)) {
> > +m
On 01/03/2018 02:59 PM, Michael Clark wrote:
> I see exit(1) called in quite a few of the other ports too. I was wondering at
> the time if there is a canonical error_abort API?
Yes, but they're wrong too. Lots of that is old code in less maintained
targets.
The only time errors should exit are
