On 12/1/2017 3:23 AM, Liu, Yi L wrote:
On Tue, Nov 14, 2017 at 06:13:49PM -0500, prasad.singamse...@oracle.com wrote:
From: Prasad Singamsetty
The current implementation of Intel IOMMU code only supports 39 bits
host/iova address width so number of macros use hard coded values based
on that.
On Tue, Nov 14, 2017 at 06:13:49PM -0500, prasad.singamse...@oracle.com wrote:
> From: Prasad Singamsetty
>
> The current implementation of Intel IOMMU code only supports 39 bits
> host/iova address width so number of macros use hard coded values based
> on that. This patch is to redefine them so
From: Prasad Singamsetty
The current implementation of Intel IOMMU code only supports 39 bits
host/iova address width so number of macros use hard coded values based
on that. This patch is to redefine them so they can be used with
variable address widths. This patch doesn't add any new functional
